Net'VectorY [0]'或直接連接的網絡由多個源驅動，並且至少有一個源是恆定網絡。 （ELAB-368）

Question

我在VCS合成器中出現這個錯誤。我嘗試了一切，但對我來說沒有意義。它表示VectorY [0]，VectorY [1]，VectorY [2]，VectorY [3]或直接連接的網絡由多個源驅動，並且至少有一個源是恆定網絡。 （ELAB-368）

module control (clk, start, S1S2mux, newDist, CompStart, PEready, VectorX, VectorY, addressR, addressS1, addressS2,completed); 

    input clk; 
    input start; 
    output reg [15:0] S1S2mux; 
    output reg [15:0] newDist; 
    output CompStart; 
    output reg [15:0] PEready; 
    output reg [3:0] VectorX,VectorY; 
    output reg [7:0] AddressR; 
    output reg [9:0] AddressS1,AddressS2; 
    reg [12:0] count; 
    output reg completed; 
    integer i; 

    assign CompStart = start; 

    always @(posedge clk) begin 
     if(start==0) begin 
      count<= 12'b0; 
      completed<=0; 
      newDist<=0; 
      PEready<=0; 
      VectorX<=0; 
      VectorY<=0; 
     end 
     else if (completed==0) 
      count <= count+1'b1; 
    end 

    always @(count) begin 
     for (i = 0; i < 15; i = i+1) 
     begin 
      newDist [i] = (count [7:0] == i); 
      PEready [i] = (newDist [i] && !(count < 8'd256)); 
      S1S2mux [i] = (count [3:0] > i); 
     end 
     addressR = count [7:0]; 
     addressS1 = (count[11:8] + count[7:4] >> 4)*5'd32 + count [3:0]; 
     addressS2 = (count[11:8] + count[7:4] >> 4)*4'd16 + count [3:0]; 
     VectorX = count[3:0] - 4'd7; 
     VectorY = count[11:8] >> 4 - 4'd7; 
     completed = (count == 4'd16 * (8'd256 + 1)); 
    end 
endmodule 

Answer 1

你或許可以這樣做...... SystemVerilog中

創建另一個邏輯變量

logic [3:0] VectorY_next; 

，然後在連續的塊，做..

always_ff begin 
     if(start==0) begin 
      count<= 12'b0; 
      completed<=0; 
      newDist<=0; 
      PEready<=0; 
      VectorX<=0; 
      VectorY<=0; 
     end 
     else if (completed==0) begin 
      count <= count+1'b1; 
      VectorY <= VectorY_next; 
     end 
end 

而在組合塊，你可以寫...

always_comb begin 
     VectorY_next = VectorY; 
     for (i = 0; i < 15; i = i+1) 
     begin 
      ..... 
     VectorY_next = count[11:8] >> 4 - 4'd7; 
     completed = (count == 4'd16 * (8'd256 + 1)); 
    end 
endmodule 

而且可能對其他端口也這樣做。要使用systemverilog運行，只需在命令行中使用-sv選項即可。