實現一個處理器（mips單週期）

我有一個迷你項目，在這個項目中我需要通過Verilog實現一個MIPS單週期處理器。這裏我寫的ALU和ALUControl和FileRegister，但我有一個問題，實施PC（程序計數器）爲此...我想這個PC支持分支和跳轉。我需要支持分支的說明，但我不知道如何訪問指令。請幫我實現InstructionMemory和Pc。這裏是我的代碼：實現一個處理器（mips單週期）

module ALU(ALUctl, A, B, ALUOut, Zero); 
input [3:0] ALUctl; 
input [31:0] A,B; 
output reg [31:0] ALUOut; 
output Zero; 
assign Zero = (ALUOut==0); //Zero is true if ALUOut is 0 
always @(ALUctl, A, B) begin //reevaluate if these change 
    case (ALUctl) 
     0: ALUOut <= A & B; 
     1: ALUOut <= A | B; 
     2: ALUOut <= A + B; 
     6: ALUOut <= A - B; 
     7: ALUOut <= A < B ? 1 : 0; 
     12: ALUOut <= ~(A | B); // result is nor 
     default: ALUOut <= 0; 
    endcase 
end

endmodule

module ALUControl(ALUOp, FuncCode, ALUCtl); 
input [1:0] ALUOp; 
input [5:0] FuncCode; 
output reg [3:0] ALUCtl; 
always @(ALUOp, FuncCode) begin 
    if (ALUOp == 2) 
     case (FuncCode) 
      32: ALUCtl<=2; // add 
      34: ALUCtl<=6; //subtract 
      36: ALUCtl<=0; // and 
      37: ALUCtl<=1; // or 
      39: ALUCtl<=12; // nor 
      42: ALUCtl<=7; // slt 
      default: ALUCtl<=15; // should not happen 
     endcase 
    else 
     case (ALUOp) 
      0: ALUCtl<=2; 
      1: ALUCtl<=6; 
      default: ALUCtl<=15; // should not happen 
     endcase 
end

endmodule

module RegFile(ra1, rd1 , ra2 , rd2 , clk , RegWrite , wa ,wd); 
input[4:0] ra1; 
output[31:0] rd1; 
input[4:0] ra2; 
output[31:0] rd2; 
input clk; 
input werf ; 
input[4:0] wa; 
input[31:0] wd; 
reg [31:0] registers[31:0]; 

assign rd1 = registers[ra1]; 
assign rd2 = registers[ra2]; 

[email protected] (posedge clk) 
    if (RegWrite) 
     registers[wa] <= wd;

endmodule

來源

2011-06-01 Rojin

你可能想看看這個stackexchange網站建議：http://area51.stackexchange.com/proposals/20632/可編程邏輯和fpga設計？referrer = PHsHo2t80NaFAaI1gMp5oQ2「可編程邏輯和FPGA設計」 – 2011-06-01 07:49:25

這裏是PC的代碼

module PC(clk , instruction , zero , branch , jump , pc); 
input clk ; 
input[31:0] instruction ; 
reg[31:0] npc; 
input zero ; 
input jump ; 
input branch ; 
wire[31:0] pcInc; 
wire[31:0] Branch1 ; 
wire[15:0] address; 
wire[31:0] branchAdd; 
reg[31:0] mux1; 
wire select1 ; 
wire[31:0] jumpAdd ; 
output [31:0] pc ; 
reg [31:0] pc ; 


assign select1 = branch & zero ; 
assign pcInc = pc + 4 ; 
assign address = instruction[15:0]; 
assign Branch1 = {{16{address[15]}},address[15:0]} ; // sign extension 
assign branchAdd = pcInc + (branch << 2) ; 

[email protected](branchAdd or pcInc or select1 ) 
begin 
    if (select1 == 1) 
     mux1 = branchAdd ; 
    else 
     mux1 = pcInc ; 
end 

assign jumpAdd = (instruction[25:0] << 2); 

[email protected] (jump or jumpAdd or mux1) 
begin 
    if (jump == 1) 
     npc = jumpAdd ; 
    else 
     npc = mux1; 
end 

always @(posedge clk) 
    pc <= npc;

endmodule

來源

2011-06-05 07:09:58 Rojin

module pc( clock , pcin , pcout , reset); 
input clock , reset; 
input [31:0] pcin ; 
output reg [31:0] pcout; 
//initial begin pcout1=0; end 
always @(posedge clock) 
begin 
    if(reset) 
     pcout = 0 ; 
    else 
     pcout = pcin ; 
end

endmodule

module InsMem(clock,RD_Address,data_out); 
input clock; 
input [31:0] RD_Address; 
output reg[31:0] data_out ; 
reg [31:0] tmp; 

    reg [31:0]mem[16:0]; 

    [email protected](posedge clock) 
    begin 
    data_out =mem[RD_Address]; 
    end

endmodule

來源

2014-05-17 08:39:46 Rojin

實現一個處理器（mips單週期）

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