展位乘法器在64位寄存器的高32位中放置1

Question

我使用展臺乘法器算法分別乘以包含在寄存器A和B中的以下數字：308和165.結果存儲在zlo和zhi中，其中zlo是低32位，zhi是高32位。以下是VHDL代碼：

variable M : std_logic_vector(64 downto 0); 
variable S : std_logic_vector(64 downto 0); 
variable P : std_logic_vector(64 downto 0); 

-- Input A is in most significant bits of M 
M(64 downto 33) := A(31 downto 0); 
M(32 downto 0) := B"00000000_00000000_00000000_00000000_0"; 
-- -Input A is in most significant bits of S 
S(64 downto 33) := std_logic_vector(NOT signed(A) + 1); 
S(32 downto 0) := B"00000000_00000000_00000000_00000000_0"; 
-- P contains the product 
P(64 downto 33) := B"00000000_00000000_00000000_00000000"; 
P(32 downto 1) := B(31 downto 0); 
P(0) := '0'; 
-- check the last two bits and perform appropriate operation and shift 
for i in 0 to 31 loop 
    if P(1 downto 0) = "01" then 
     P(64 downto 0) := std_logic_vector(signed(P) + signed(M)); 
    elsif P(1 downto 0) = "10" then 
     P(64 downto 0) := std_logic_vector(signed(P) + signed(S)); 
    end if; 
    P := std_logic_vector(signed(P) srl 1); 
end loop; 
zhi <= P(64 downto 33); 
zlo <= P(32 downto 1); 

ModelSim中波形的結果如下所示。正如你所看到的，308被裝載到公共汽車上，然後是165.結果，50820然後被存儲在總線（zlo）上，然後1被存儲在總線（zhi）上。爲什麼有1？ 50820不會進入高32位。

Answer 1

嗯，當我複製你的代碼，它也沒有爲我工作。所以我把它清理了很多，現在它可以工作......但是我不知道我改變了什麼使它能夠工作。也許別人可以幫忙？這可能與算術有關。

library ieee; use ieee.std_logic_1164.all;

entity booth_mult is 
    generic(
     nr_of_bits : positive := 32 
     ); 
    port(
     clk : in std_logic; 
     A : in integer; 
     B : in integer; 
     zhi : out std_logic_vector(nr_of_bits-1 downto 0); 
     zlo : out std_logic_vector(nr_of_bits-1 downto 0) 
     ); 
end entity booth_mult; 

library ieee; 
use ieee.numeric_std.all; 

architecture behavior of booth_mult is 
    signal M : signed((2*nr_of_bits) downto 0) := (others => '0'); 
    signal S : signed((2*nr_of_bits) downto 0) := (others => '0'); 
    signal P : signed((2*nr_of_bits) downto 0) := (others => '0'); 

    signal index : natural := 0; 
begin 
-- check the last two bits and perform appropriate operation and shift 
    clk_booth : process(clk) 
     variable P_temp : signed(P'range); 
    begin 
     if rising_edge(clk) then 
      if index = 0 then 
       M((2*nr_of_bits) downto nr_of_bits+1) <= to_signed(A, nr_of_bits); 
       S((2*nr_of_bits) downto nr_of_bits+1) <= to_signed(-A, nr_of_bits); 
       P(nr_of_bits downto 1) <= to_signed(B, nr_of_bits); 
      elsif index < (nr_of_bits+1) then 
       P_temp := P; 
       if P(1 downto 0) = "01" then 
        P_temp := P + M; 
       elsif P(1 downto 0) = "10" then 
        P_temp := P + S; 
       end if; 
       P <= shift_right(P_temp, 1); 
      end if; 
      index <= index + 1; 
     end if; 
    end process; 

    zhi <= std_logic_vector(P((2*nr_of_bits) downto nr_of_bits+1)); 
    zlo <= std_logic_vector(P(nr_of_bits downto 1)); 
end architecture; 

和測試平臺

entity booth_mult_tb is 
end entity booth_mult_tb; 

library ieee; 
use ieee.std_logic_1164.all; 

architecture behavior of booth_mult_tb is 
    signal clk : std_logic := '0'; 

    constant nr_of_bits : positive := 32; 

    constant A : integer := 308; 
    constant B : integer := 165; 

    signal zhi : std_logic_vector(nr_of_bits-1 downto 0); 
    signal zlo : std_logic_vector(nr_of_bits-1 downto 0); 
begin 
    dut : entity work.booth_mult 
     generic map(
      nr_of_bits => nr_of_bits 
      ) 
     port map(
      clk => clk, 
      A => A, 
      B => B, 
      zhi => zhi, 
      zlo => zlo 
      ); 

    clk_proc : process 
    begin 
     loop 
      clk <= '0', '1' after 1 ns; 
      wait for 2 ns; 
     end loop; 
    end process; 
end architecture;