基於LUT4組件的LUT5組件的結構描述

Question

請告訴我如何根據LUT4組件正確描述LUT5的結構組件，問題恰恰在於端口的正確映射。

Entity LUT5 is 
Port(
    A,B,C,D,E : in std_logic; 
    Z   : out std_logic; 
); 
End LUT5; 

Architecture Behaviour of LUT5 is 
Component LUT4 
Port(
    A,B,C,D : in std_logic; 
    Z  : out std_logic; 
); 
End Component; 
Begin 
    ?????? 
End 
End Architecture 

Answer 1

可以通過使用兩個四輸入的查找表與基於第五位的輸出之間的選擇器選擇表示一個五個輸入的查找表：

library ieee; 
use ieee.std_logic_1164.all; 

entity lut5 is 
    generic (
     LUTVAL: std_logic_vector (0 to 31) 
    ); 
    port (
     a, b, c, d, e: in std_logic; 
     z :    out std_logic 
    ); 
end entity lut5; 

architecture behaviour of lut5 is 
    component mux2 is 
     port (
      a: in std_logic; 
      b: in std_logic; 
      s: in std_logic; 
      y: out std_logic 
     ); 
    end component; 
    component lut4 is 
     generic (
      LUTVAL: std_logic_vector (0 to 15) 
     ); 
     port (
      a, b, c, d: in std_logic; 
      z:   out std_logic 
     ); 
    end component; 
    signal z0, z1:  std_logic; 
begin 
LUT4_0: 
    lut4 
     generic map (
      LUTVAL => LUTVAL(0 to 15) 
     ) 
     port map (
      a => a, 
      b => b, 
      c => c, 
      d => d, 
      z => z0 
     ); 
LUT4_1: 
    lut4 
     generic map (
      LUTVAL => LUTVAL(16 to 31) 
     ) 
     port map (
      a => a, 
      b => b, 
      c => c, 
      d => d, 
      z => z1 
     ); 
MUX_2_1: 
    mux2 
     port map (
      a => z0, 
      b => z1, 
      s => e, 
      y => z 
     ); 
end architecture; 

的泛型是遞送的方法從設計模型的頂層查找表格內容。

它添加一個小的測試平臺：

library ieee; 
use ieee.std_logic_1164.all; 

entity lut5_tb is 
end entity; 

architecture foo of lut5_tb is 
    signal a, b, c, d, e: std_logic := '0'; 
    signal z:    std_logic; 
    constant LUTVAL:  std_logic_vector (0 to 31) := x"A2201000"; 
    signal index:   natural; 
begin 
DUT: 
    entity work.lut5 
    generic map (
     LUTVAL => LUTVAL 
    ) 
    port map (
     a => a, 
     b => b, 
     c => c, 
     d => d, 
     e => e, 
     z => z 
    ); 
STIMULI: 
    process 
     use ieee.numeric_std.all; 
    begin 
     for i in LUTVAL'RANGE loop 
      (e, d, c, b, a) <= to_unsigned(i,5); 
      index <= i; 
      wait for 10 ns; 
     end loop; 
     wait; 
    end process; 
end architecture; 

而且我們可以看到，它執行了五個輸入查找表：

您可以在Z輸出端在數位時間使用添加的索引信號並查找輸出重建32位LUTVAL（x「A2201000」）。

這裏是失蹤的點點滴滴：

library ieee; 
use ieee.std_logic_1164.all; 

entity mux2 is 
    port (
     a: in std_logic; 
     b: in std_logic; 
     s: in std_logic; 
     y: out std_logic 
    ); 
end entity; 

architecture foo of mux2 is 
begin 
    y <= a when s = '0' else 
     b; 
end architecture; 

library ieee; 
use ieee.std_logic_1164.all; 

entity lut4 is 
    generic (
     LUTVAL: std_logic_vector (0 to 15) 
    ); 
    port (
     a, b, c, d: in std_logic; 
     z:   out std_logic 
    ); 
end entity; 

architecture foo of lut4 is 
    constant lut: std_logic_vector := LUTVAL; 
    use ieee.numeric_std.all; 
begin 
LOOKUP: 
    z <= lut(to_integer(unsigned'(d,c,b,a))); 
end architecture;