Verilog中的端口大小錯誤：[PCDPC] - 端口大小不匹配端口的連接大小（1）

Question

這些是我對單週期處理器的不同部分的代碼，但我在實例化中收到以下警告。請幫我找到這個錯誤，因爲這種錯誤經常發生

module reg_file(reg_addr_1,reg_addr_2,write_en,RD1,RD2,write_data,reg_addr_1,reg_addr_2,clk,wr_addr); 
input clk; 
input[3:0] reg_addr_1,reg_addr_2; 
input [3:0] wr_addr; 
input [15:0]write_data; 
input write_en; 
output [15:0]RD1,RD2; 
reg [15:0]rgs[0:15]; 

assign RD1=rgs[reg_addr_1]; 
assign R22=rgs[reg_addr_2]; 

always@(posedge clk) 
begin 
if(write_en) 
rgs[wr_addr] <= write_data; 
end 
endmodule 





module alu(cout,alu_output,input1,input2,alu_sel); 
input [15:0]input1,input2; 
input [3:0]alu_sel; 
output [15:0]alu_output; 
output cout; 
reg [15:0]alu_output; 
reg cout; 
always@(input1,input2,alu_sel) 
begin 
case(alu_sel) 
4'b0000 : {cout,alu_output}=input1+input2; 
4'b0001 : {cout,alu_output}=input1-input2; 
4'b0010 : alu_output=input2-1; 
4'b0011 : alu_output=input1*input2; 
4'b0100 : alu_output=input1&&input2; 
4'b0101 : alu_output=input1||input2; 
4'b0110 : alu_output= !input1; 
4'b0111 : alu_output=~input1; 
4'b1000 : alu_output=input1&input2; 
4'b1001 : alu_output=input1|input2; 
4'b1010 : alu_output=input1^input2; 
4'b1011 : alu_output=input1<<1; 
4'b1100 : alu_output=input1>>1; 
4'b1101 : alu_output=input1+1; 
4'b1110 : alu_output=input1-1; 
4'b1111 : alu_output=input2<<1; 
endcase 
end 
endmodule 




module reg_alu(clk,out); 
input clk; 
output [15:0] out; 

alu a1(cout,out,RD1,RD2,alu_sel); 
reg_file a2(reg_addr_1,reg_addr_2,write_en,RD1,RD2,alu_output,reg_addr_1,reg_addr_2,clk,wr_addr); 
endmodule 






module tb_aaaa; 
reg clk; 
wire alu_output; 
wire [15:0]out; 
reg write_en; 
reg [15:0]input1,input2; 
reg [3:0]alu_sel; 
reg_alu tb_aaaa(clk,out); 
initial 
begin 
#10 clk=1'b1;write_en=1'b0;input1=16'b0000000101010101;input2=16'b0000000000111111;alu_sel=4'b0010; 
#10 clk=1'b0;write_en=1'b1;input2=16'b0000000101010101;input2=16'b0000000000111100;alu_sel=4'b0011; 
end 
initial begin 
$monitor($time,"clk,out,write_data",clk,out); 
end 
initial 
begin 
#300 $stop; 
end 
endmodule 

這些都是我從編譯器得到警告

 ** Warning: (vsim-3015) C:/Users/Saeed/Desktop/project/reg_alu.v(5): [PCDPC] - Port size (16 or 16) does not match connection size (1) for port 'input1'. 
    #   Region: /tb_aaaa/tb_aaaa/a1 
    # ** Warning: (vsim-3015) C:/Users/Saeed/Desktop/project/reg_alu.v(5): [PCDPC] - Port size (16 or 16) does not match connection size (1) for port 'input2'. 
    #   Region: /tb_aaaa/tb_aaaa/a1 
    # ** Warning: (vsim-3015) C:/Users/Saeed/Desktop/project/reg_alu.v(5): [PCDPC] - Port size (4 or 4) does not match connection size (1) for port 'alu_sel'. 
    #   Region: /tb_aaaa/tb_aaaa/a1 
    # ** Warning: (vsim-3015) C:/Users/Saeed/Desktop/project/reg_alu.v(6): [PCDPC] - Port size (4 or 4) does not match connection size (1) for port 'reg_addr_1'. 
    #   Region: /tb_aaaa/tb_aaaa/a2 
    # ** Warning: (vsim-3015) C:/Users/Saeed/Desktop/project/reg_alu.v(6): [PCDPC] - Port size (4 or 4) does not match connection size (1) for port 'reg_addr_2'. 
    #   Region: /tb_aaaa/tb_aaaa/a2 
    # ** Warning: (vsim-3015) C:/Users/Saeed/Desktop/project/reg_alu.v(6): [PCDPC] - Port size (16 or 16) does not match connection size (1) for port 'RD1'. 
    #   Region: /tb_aaaa/tb_aaaa/a2 
    # ** Warning: (vsim-3015) C:/Users/Saeed/Desktop/project/reg_alu.v(6): [PCDPC] - Port size (16 or 16) does not match connection size (1) for port 'RD2'. 
    #   Region: /tb_aaaa/tb_aaaa/a2 
    # ** Warning: (vsim-3015) C:/Users/Saeed/Desktop/project/reg_alu.v(6): [PCDPC] - Port size (16 or 16) does not match connection size (1) for port 'write_data'. 
    #   Region: /tb_aaaa/tb_aaaa/a2 
    # ** Warning: (vsim-3015) C:/Users/Saeed/Desktop/project/reg_alu.v(6): [PCDPC] - Port size (4 or 4) does not match connection size (1) for port 'reg_addr_1'. 
    #   Region: /tb_aaaa/tb_aaaa/a2 
    # ** Warning: (vsim-3015) C:/Users/Saeed/Desktop/project/reg_alu.v(6): [PCDPC] - Port size (4 or 4) does not match connection size (1) for port 'reg_addr_2'. 
    #   Region: /tb_aaaa/tb_aaaa/a2 
    # ** Warning: (vsim-3015) C:/Users/Saeed/Desktop/project/reg_alu.v(6): [PCDPC] - Port size (4 or 4) does not match connection size (1) for port 'wr_addr'. 
    #   Region: /tb_aaaa/tb_aaaa/a2 

Answer 1

你的一個問題是，你正在使用的電線沒有宣佈它們的寬度。當你使用一個名稱而不聲明它在一個端口連接中時，Verilog會有一個令人討厭的行爲，它假定它是一個一位線。當人們進行門級描述時，這很好，大部分線路都是一點，但不適用於RTL。所以把這個指令放在每個文件的開頭

`default_nettype none