modelsim說：「接近」）「：（vcom-1576）期待IDENTIFIER。」在編譯

Question

我剛纔寫的：

library ieee; 
use ieee.std_logic_1164.all; 

entity and_gate is 
port(
    input_1 : in std_logic; 
    input_2 : in std_logic; 
    and_result : out std_logic; 
); 
end and_gate; 

architecture rtl of and_gate is 
signal and_gate : std_logic; 
begin 
    and_gate <= input_1 and input_2; 
    and_result <= and_gate; 
end rtl; 

當我編譯時，ModelSim的編譯器給了我這個錯誤：

** Error: C:/modeltech64_10.5/examples/and_gate.vhd(8): near ")": (vcom-1576) expecting IDENTIFIER. 

我搜索並嘗試了一些解決方案，但我仍然得到錯誤。

Answer 1

這

and_result : out std_logic; 

應該是這個

and_result : out std_logic