GtkWave不是從IVerilog模擬信號越來越

Question

我寫了下面的測試我的代碼：

module HalfAdder_Test; 
wire sum; 
wire carry; 
reg a = 0; 
reg b = 0; 

initial begin 
    $dumpfile("test.vcd"); 
    $dumpvars(0, HalfAdder_Test); 

    # 10 a = 0; 
    # 10 b = 0; 

    # 30 a = 1; 
    # 30 b = 0; 

    # 50 a = 0; 
    # 50 b = 1; 

    # 70 a = 1; 
    # 70 b = 1; 

    # 90 $stop; 
end 

HalfAdder ha (a, b, sum, carry); 
endmodule 

我然後編譯它，使用下面的命令在GTKWave打開它：

iverilog -o HalfAdder -c files.txt 
vvp HalfAdder -lxt2 
gtkwave output.vcd 

當我這樣做，我得到以下輸出：

問題是，即使他們在模擬中，我的信號也不會很高。什麼可能導致我的模擬不輸出？

當我打開我的.vcd文件，我得到下面的輸出：

1380 0001 4000 0000 0800 0000 9a00 0000 
1400 0000 4400 0000 3800 0000 2300 1f8b 
0800 0000 0000 020b 6360 f048 cc49 734c 
4949 2d8a 0f49 2d2e d14b 6460 e04f 02e2 
e4c4 a2a2 4a20 5d5c 9a0b 2433 12f5 1c19 
1884 9c80 d819 8883 1900 93ef 3630 3800 
0000 1f8b 0800 0000 0000 020b 6360 a02a 
e000 6246 343e 131a 9f19 990f 003c 2732 
3f80 0000 0000 0000 6a00 0000 5800 0000 
0000 0000 0000 0000 0000 0000 fa1f 8b08 
0000 0000 0000 0b62 6065 4005 4650 ba09 
4a6f 81d2 bf00 0000 00ff ff62 6460 6462 
6604 0000 00ff ff62 6062 6262 0043 2000 
0000 00ff ff62 0400 0000 ffff 83ca 8943 
694e 282d 08a5 e5a1 3408 b000 003e bbb2 
446a 0000 0000 0000 2900 0000 3f00 0000 
0000 0001 9a00 0000 0000 0001 9a1f 8b08 
0000 0000 0000 0b62 6064 0003 c659 0000 
0000 ffff 0233 1801 0000 00ff ff02 0206 
0000 0000 ffff 6204 0000 00ff ff83 08c1 
6930 1b00 c899 14b8 2900 0000 

Answer 1

的問題是，在觀看模擬的時間尺度。

Answer 2

module tb_top 
(
    top_clk, 
    top_rst 
); 

    input top_clk; 
    input top_rst; 

    reg thirty; 
    reg twenty; 
    reg [31:0]SHOW_CLK; 

    always @(posedge top_clk or negedge top_rst) 
    begin 
     if (top_rst==1'b0) 
     begin 
      SHOW_CLK <= 32'h0; 
      twenty <= 1'h0; 
      thirty <= 1'h0; 
     end 
     else 
     begin 
      SHOW_CLK <= (SHOW_CLK+32'h1); 
      twenty <= 1'h0; 
      thirty <= 1'h0; 
      if ((SHOW_CLK==32'h14)) 
      begin 
       twenty <= 1'h1; 
      end 
      if ((SHOW_CLK==32'h1e)) 
      begin 
       thirty <= 1'h1; 
      end 
     end 
    end 

endmodule 

這是一個VCD文件的樣子，他們用工具，以快捷方式的名稱是什麼改變（d是在這種情況下SHOW_CLK）

$scope module tb_top0 $end 
$var wire 32 D SHOW_CLK $end 
$var wire 1 B thirty $end 
$var wire 1 E top_rst $end 
$var wire 1 C twenty $end 
$enddefinitions $end 
#0 
b00000000000000000000000000000000 D 
0B 
0E 
0C 
#20 
b00000000000000000000000000000001 D 
1E 
#22 
b00000000000000000000000000000010 D 
#24 
b00000000000000000000000000000011 D 
#26 
b00000000000000000000000000000100 D 
#28 
b00000000000000000000000000000101 D 
#30 
b00000000000000000000000000000110 D 
#32 
b00000000000000000000000000000111 D 
#34 
b00000000000000000000000000001000 D 
#36 
b00000000000000000000000000001001 D 
#38 
b00000000000000000000000000001010 D 
#40 
b00000000000000000000000000001011 D 
#42 
b00000000000000000000000000001100 D 
#44 
b00000000000000000000000000001101 D 
#46 
b00000000000000000000000000001110 D 
#48 
b00000000000000000000000000001111 D 
#50 
b00000000000000000000000000010000 D 
#52 
b00000000000000000000000000010001 D 
#54 
b00000000000000000000000000010010 D 
#56 
b00000000000000000000000000010011 D 
#58 
b00000000000000000000000000010100 D 
#60 
b00000000000000000000000000010101 D 
1C 
#62 
b00000000000000000000000000010110 D 
0C 
#64 
b00000000000000000000000000010111 D 
#66 
b00000000000000000000000000011000 D 
#68 
b00000000000000000000000000011001 D 
#70 
b00000000000000000000000000011010 D 
#72 
b00000000000000000000000000011011 D 
#74 
b00000000000000000000000000011100 D 
#76 
b00000000000000000000000000011101 D 
#78 
b00000000000000000000000000011110 D 
#80 
b00000000000000000000000000011111 D 
1B 
#82 
b00000000000000000000000000100000 D 
0B 
#84 
b00000000000000000000000000100001 D 
#86 
b00000000000000000000000000100010 D 
#88 
b00000000000000000000000000100011 D 
#90 
b00000000000000000000000000100100 D 
#92 
b00000000000000000000000000100101 D 
#94 
b00000000000000000000000000100110 D 
#96 
b00000000000000000000000000100111 D 
#98 
b00000000000000000000000000101000 D 

如果你到的定義到底也許是＃0但沒有時鐘數據，這可能意味着你的設計實際上並沒有改變任何選定信號的狀態（這可能是因爲你的設計或者你沒有足夠長的時間運行SIM）。

VCD是一種ascii文件格式，與您最近的成功無關，您應該嘗試弄清楚如何查找文本文件（例如使用編輯verilog的相同文本編輯器）。