JK觸發器代碼調試

Question

以下爲JK觸發器的代碼： -

entity jkasync is 
Port (j : in std_logic; 
     k : in std_logic; 
     r : in std_logic; 
     clk : in std_logic; 
     q : inout std_logic); 
end jkasync; 

architecture Behavioral of jkasync is 
signal s: std_logic_vector(1 downto 0); 
s <= j&k; 
begin 

    process (j,k,r,clk) 
    begin 

     if (r='1') then 
     q<='0'; 
     elsif (falling_edge(clk)) then 
     case s is 
     when "00" =>q<=q; 
     when "01" =>q<='0'; 
     when "10" =>q<='1'; 
     when "11" =>q<= not q; 
     when others =>q<='0'; 
     end case; 
     end if; 
    end process; 


    end Behavioral; 

而且我收到以下錯誤： -

線21.解析錯誤，意想不到的標識符

21行是s<=j&k; 所以，請幫助我更正此代碼的語法，並請告訴我這裏有什麼問題。 謝謝。

Answer 1

明白了。

一個新的信號在體系結構體中被初始化，但是這個值是在過程體內定義的。

SO移動過程中的21行。

正確的代碼： -

architecture Behavioral of jkasync is 
    signal s: std_logic_vector(1 downto 0); 

    begin 
    s <= j&k; 
    process (j,k,r,clk) 
    begin 

     if (r='1') then 
     q<='0'; 
     elsif (falling_edge(clk)) then 
     case s is 
     when "00" =>q<=q; 
     when "01" =>q<='0'; 
     when "10" =>q<='1'; 
     when "11" =>q<= not q; 
     when others =>q<='0'; 
     end case; 
     end if; 
    end process; 


     end Behavioral;