我正在使用JK觸發器編寫2位計數器的verilog代碼,計數0-3並返回0.我使用Xilinx EDA。但是我一直在收到一個錯誤,我不知道它是什麼意思?行號不顯示在這裏,但錯誤位於「always @(posedge clk)
」。在Verilog中使用JK觸發器的2位計數器
ERROR:HDLCompiler:1401 - "C:\Users\Eduardo\Documents\SFSU\Fall 2014\Engr 378\Lab 3\TwoBitCounter\twobitcounter.v" Line 30: Signal q in unit jkff is connected to following multiple drivers:
`timescale 1ns/1ps
module twobitcounter(q_out, qbar_out, j,k, clk, reset);
input [1:0] j; input [1:0] k; input clk; input reset;
output [1:0] q_out;
output [1:0] qbar_out;
wire [1:0] q_out;
wire [1:0] qbar_out;
wire clk;
assign qbar_out[0] = ~q_out[0];
assign j[0] = 1;
assign k[0] = 1;
assign j[1] = q_out[0];
assign k[1] = q_out[0];
jkff M1(q_out[0], qbar_out[0], j[0], k[0], clk, reset);
jkff M2(q_out[1], qbar_out[1], j[1], k[1], qbar_out[0]);
endmodule
module jkff(output q_out, output qbar_out,
input j, input k, input clk, input reset);
reg q;
assign q_out = q;
assign qbar_out = ~q;
initial begin
q = 1'b0;
end
always @(posedge clk)
begin
case({j,k})
{1'b0, 1'b0}: begin
q = q;
end
{1'b0, 1'b1}: begin
q = 1'b0;
end
{1'b1, 1'b0}: begin
q = 1'b1;
end
{1'b1, 1'b1}: begin
q = ~q;
end
endcase
end
always @(posedge reset)
begin
q = 1'b0;
end
endmodule
**幾乎從不使用初始塊(在某些情況下,大多數FPGA的綜合工具都允許初始塊,如初始化存儲器元素)。而且,q也被分配在@(posedge reset)塊中。 – Unn 2014-10-02 19:27:55