如何將樹狀結構中的位置標識轉換爲其位置標識？ Verilog

在這個二進制特里結構的位置ID中，左子元素將取0，右子取1。所以0級是根0，1級是元素1和2（0的兩個子），3級是3,4（兩個1的兒子），5和6（2的兩個兒子）。對於位置id 6，位置id將是11.（第一個是0的右邊兒子，第二個是2的右邊兒子）。我想知道在一個時鐘中將位置標識（如6）轉換爲其位置標識（11）的方式是什麼，或者至少是更好的方法。如何將樹狀結構中的位置標識轉換爲其位置標識？ Verilog

例如：

6 --> 11 

12 --> 101

謝謝

Picture for the trie structure

來源

2016-05-17 raymondxuym

你能以圖形呈現您的方案，或給予更多的解釋？ –

你可以向你展示一個trie的verilog實現嗎？這可能有助於指導答案，因爲它目前非常抽象。 – Morgan

@PrakashDarji謝謝你的回覆，我爲這個trie創建了一個圖片，在這種情況下，如果給定數字13，我們怎麼能得到110？ – raymondxuym

認爲，不支持可變輸出寬度，見婁代碼，它可以幫助你。

module find_id ( 
       input wire [3:0] loc_id, // 1 to 14 
       output reg [2:0] pos_id 
       ); 

reg pos_1, pos_2, pos_3; 

always @ (*) 
begin 
    pos_1 = (loc_id == 4'd2) 
     | (loc_id == 4'd5 | (loc_id == 4'd6)) 
     | (loc_id >= 11); 

    pos_2 = (pos_1 & ((loc_id == 4'd6) | (loc_id == 4'd13) | (loc_id == 4'd14))) 
     | (~pos_1 & ((loc_id == 4'd4) | (loc_id == 4'd9 ) | (loc_id == 4'd10))); 

    pos_3 = (pos_1 & pos_2 & (loc_id == 4'd14)) 
     | (pos_1 & ~pos_2 & (loc_id == 4'd12)) 
     | (~pos_1 & pos_2 & (loc_id == 4'd10)) 
     | (~pos_1 & ~pos_2 & (loc_id == 4'd8)); 
end 


always @ (*) 
begin 
    pos_id = ({3{(loc_id <= 4'd2)     }} & {pos_1, 1'bx, 1'bx}) 
     | ({3{(loc_id <= 4'd6) & (loc_id >= 4'd3)}} & {pos_1,pos_2, 1'bx}) 
     | ({3{(loc_id <= 4'd14) & (loc_id >= 4'd7)}} & {pos_1,pos_2,pos_3}) ; 
end 

endmodule

爲了驗證看到TB：

module tb; 

reg [3:0] loc_id; 
wire [2:0] pos_id; 

find_id find_id_0(loc_id, pos_id); 

initial 
begin 
    loc_id = 4'b0; 
    #100 loc_id = 4'd10; 
    #100 loc_id = 4'd9; 
    #100 loc_id = 4'd13; 
    #100 loc_id = 4'd6; 
    #100 loc_id = 4'd8; 
    #100 loc_id = 4'd11; 
    #100 loc_id = 4'd7; 
    #100 loc_id = 4'd4; 
    #100 loc_id = 4'd12; 
    #100 $finish; 
end 

initial 
    $monitor ("loc_id = %d pos_id =%b",loc_id, pos_id); 

endmodule

仿真結果後會是這樣的：

# 10.4 

# vsim -lib work tb -c -do "run -all; quit -f" -appendlog -l qverilog.log -vopt 
# ** Note: (vsim-3813) Design is being optimized due to module recompilation... 
# // Questa Sim-64 
# // Version 10.4 linux_x86_64 Dec 2 2014 
# // 
# // Copyright 1991-2014 Mentor Graphics Corporation 
# // All Rights Reserved. 
# // 
# // THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION 
# // WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS 
# // LICENSORS AND IS SUBJECT TO LICENSE TERMS. 
# // THIS DOCUMENT CONTAINS TRADE SECRETS AND COMMERCIAL OR FINANCIAL 
# // INFORMATION THAT ARE PRIVILEGED, CONFIDENTIAL, AND EXEMPT FROM 
# // DISCLOSURE UNDER THE FREEDOM OF INFORMATION ACT, 5 U.S.C. SECTION 552. 
# // FURTHERMORE, THIS INFORMATION IS PROHIBITED FROM DISCLOSURE UNDER 
# // THE TRADE SECRETS ACT, 18 U.S.C. SECTION 1905. 
# // 
# Loading work.tb(fast) 
# run -all 
# loc_id = 0 pos_id =0xx 
# loc_id = 10 pos_id =011 
# loc_id = 9 pos_id =010 
# loc_id = 13 pos_id =110 
# loc_id = 6 pos_id =11x 
# loc_id = 8 pos_id =001 
# loc_id = 11 pos_id =100 
# loc_id = 7 pos_id =000 
# loc_id = 4 pos_id =01x 
# loc_id = 12 pos_id =101 
# ** Note: $finish : find_id.v(56) 
# Time: 1 us Iteration: 0 Instance: /tb 
# End time: 09:58:04 on May 18,2016, Elapsed time: 0:00:01 
# Errors: 0, Warnings: 0

來源

2016-05-18 04:31:29

嗨Prakash：非常感謝你的整潔的代碼和驗證！這看起來非常棒！ – raymondxuym

我又試了一次：用位置ID中的第一個數字減去位置ID，然後我們得到位置ID。例如：對於ID 12，我們得到1100 - 111 = 101. 101是12的位置ID – raymondxuym

如果您發現此答案有效thqn接受它作爲答案 –

如何將樹狀結構中的位置標識轉換爲其位置標識？ Verilog

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