3
我在鑿子代碼中得到以下異常。在鑿子內存中不存在可綜合節點異常
[info] - should correctly write and read data *** FAILED ***
[info] chisel3.core.Binding$BindingException: 'this' ([email protected]): Not bound to synthesizable node, currently only Type description
[info] at chisel3.core.Binding$.checkSynthesizable(Binding.scala:184)
[info] at chisel3.core.Data.connect(Data.scala:139)
[info] at chisel3.core.Data.$colon$eq(Data.scala:204)
[info] at Common.OnChipMemory$$anonfun$1.apply(memory.scala:88)
[info] at Common.OnChipMemory$$anonfun$1.apply(memory.scala:60)
[info] at scala.collection.immutable.Range.foreach(Range.scala:166)
[info] at Common.OnChipMemory.<init>(memory.scala:60)
[info] at Common.memoryTester$$anonfun$3$$anonfun$apply$1$$anonfun$apply$mcV$sp$1.apply(memoryTest.scala:32)
[info] at Common.memoryTester$$anonfun$3$$anonfun$apply$1$$anonfun$apply$mcV$sp$1.apply(memoryTest.scala:32)
[info] at chisel3.core.Module$.do_apply(Module.scala:35)
從這個堆棧跟蹤和一些試驗和錯誤的測試我能找到該行，
read_data := chipMem(data_idx) //line 88
引起的問題。緊接着的代碼在下面發佈。
val lsb_idx = log2Up(4) // index of lsb in address
val chipMem = Mem(Vec(4, UInt(width = 8)), num_lines) // memory
val data_idx = req_addr >> UInt(lsb_idx) //req_addr is a UInt
val read_data = Bits()
之後我找不到問題的原因。我嘗試將read_data更改爲UInt的Vec，並使用read（）從內存中讀取。