Verilog FIR濾波器代碼錯誤

Question

我遇到了我的FIR信號輸出問題。信號不會被濾除，並且會有很多靜態信號。雖然我的實現似乎工作正常。我的乘數函數是從quartus軟件中的現有庫創建的，並被設置爲有符號乘法。我真的不知道發生了什麼，並會感謝任何幫助！謝謝！

代碼：

`timescale 1ns/1ps 
module fir_filter (input sample_clock, input reset, input [15:0]  input_sample1,  output [15:0] output_sample1); 

parameter N = 65; //Specify the number of taps 

reg [15:0] delayholder[N-1:0]; 

wire [31:0] summation[N-1:0]; 

wire [15:0] finsummations[N-1:0]; 
wire [15:0] finsummation; 

integer x; 
integer z; 

//Specifying our coefficients 
reg signed[15:0] coeffs[200:0]; 


always @(*) 
begin 

for (x=0; x<N; x=x+31) 
begin 

coeffs[x+0] = 0; 
coeffs[x+1] = 2267; 
coeffs[x+2] = 0; 
coeffs[x+3] = -3030; 
coeffs[x+4] = 0; 
coeffs[x+5] = 4621; 
coeffs[x+6] = 0; 
coeffs[x+7] = -6337; 
coeffs[x+8] = 0; 
coeffs[x+9] = 7985; 
coeffs[x+10] = 0; 
coeffs[x+11] = -9536; 
coeffs[x+12] = 1; 
coeffs[x+13] = 10265; 
coeffs[x+14] = -1; 
coeffs[x+15] = 87720; 
coeffs[x+16] = -1; 
coeffs[x+17] = 10265; 
coeffs[x+18] = 1; 
coeffs[x+19] = -9536; 
coeffs[x+20] = 0; 
coeffs[x+21] = 7985; 
coeffs[x+22] = 0; 
coeffs[x+23] = -6337; 
coeffs[x+24] = 0; 
coeffs[x+25] = 4621; 
coeffs[x+26] = 0; 
coeffs[x+27] = -3030; 
coeffs[x+28] = 0; 
coeffs[x+29] = 2267; 
coeffs[x+30] = 0; 
end 
end 

generate 
genvar i; 
for (i=0; i<N; i=i+1) 
begin: mult1 
    multiplier mult1(.dataa(coeffs[i]),  .datab(delayholder[i]),.result(summation[i])); 
end 
endgenerate 

always @(posedge sample_clock or posedge reset) 
begin 
if(reset) 
    begin 
     output_sample1 = 0; 
     for (z=0; z<N; z=z+1) 
     begin 
     delayholder[z] = 0; 
     end 
end 

else 
    begin 
     for (z=N-1; z>0; z=z-1) 
     begin 
     delayholder[z] = delayholder[z-1]; 
     end 
     delayholder[0] = input_sample1; 
end 

    for (z=0; z<N; z=z+1) 
    begin 
    finsummations[z] = summation[z] >> 15; //{summation[z][15],  summation[z][15], summation[z][15:2]} 
    end 

     finsummation = 0; 
    for (z=0; z<N; z=z+1) 
     begin 
     finsummation = finsummation + finsummations[z]; 
     end 

     output_sample1 = finsummation; 
end 

endmodule 

乘數代碼：

`timescale 1 ps/1 ps 
module multiplier (dataa,datab,result); 

input [15:0] dataa; 
input [15:0] datab; 
output [31:0] result; 

wire [31:0] sub_wire0; 
wire [31:0] result = sub_wire0[31:0]; 

lpm_mult lpm_mult_component (
      .dataa (dataa), 
      .datab (datab), 
      .result (sub_wire0), 
      .aclr (1'b0), 
      .clken (1'b1), 
      .clock (1'b0), 
      .sum (1'b0)); 
defparam 
    lpm_mult_component.lpm_hint = "MAXIMIZE_SPEED=5", 
    lpm_mult_component.lpm_representation = "SIGNED", 
    lpm_mult_component.lpm_type = "LPM_MULT", 
    lpm_mult_component.lpm_widtha = 16, 
    lpm_mult_component.lpm_widthb = 16, 
    lpm_mult_component.lpm_widthp = 32; 

Answer 1

我對過濾器專家，但我看到一對夫婦的潛在問題，用來初始化係數的代碼塊。首先，我建議將它作爲初始塊，因爲它只需要真正發生一次。其次，使用16位有符號值，您的範圍爲-32767至+32768，但其中一個係數爲87720，超出範圍。由於Verilog不像VHDL那樣強類型化，你可以這樣做，但結果不會是你想要的。您可能需要更改係數值或增加係數的位寬，並更改您的乘法器代碼以使用更大的寬度。最後，你指定了201個係數，但是你的賦值邏輯只是給coeffs 0到92賦值。這應該在你的模擬中顯示爲一串「X」（你在模擬中試過這個，對吧？ ）。綜合你的設計時，你的工具應該抱怨，但它可能只是給初始化位置賦值爲零（賽靈思的Vivado做到這一點，我不知道其他工具如何）。無論如何，你希望實現的目標與該工具將產生的目標之間存在差異。