-1
我有這個代碼,它早期產生一個GTK波,但我必須從行爲上使它RTL,但現在它不會編譯。如果任何人能幫助我想出解決辦法,我得到錯誤:Verilog倍數不會編譯
- main.v:31:錯誤:格式不正確的說法
- main.v:26:錯誤:在for循環步分配
- main.v:26:語法錯誤
- main.v:30:語法錯誤
- main.v:30:錯誤:格式不正確的說法
- main.v:31:語法錯誤
這裏是我的代碼:
module combinational_mult(product,multiplier,multiplicand);
input [31:0] multiplier;
input [63:0] multiplicand;
output product;
reg [63:0] product;
reg c;
reg [63:0] m;
integer i;
always @(multiplier or multiplicand)
begin
//initialize
product[63:32] = 32'b0;
product[31:0] = multiplier;
m = multiplicand;
c = 1'b0;
//add,shift algorithm for unsigned multiplication.
//following the notes.
// for(i=0; i<32; i=i+1)
// begin
//if(product[0]) {c,product[63:32]} = product[31:16] + m ;
//product[63:0] = {c,product[63:1]};
// c = 0;
for (i = 0; i < 32; i++)
begin
if (multiplier == 1)
product = product + m;
multiplicand << 1;
multiplier >> 1;
c=0;
end
end
endmodule
module testbench;
reg [31:0] multiplier;
reg [63:0] multiplicand;
initial begin
$dumpfile("USAMv1.dat");
$dumpvars;
#10ns;
multiplier = 32'b0000_0000_0000_0000_1101_1001_1101_1001;
multiplicand = 32'b0000_0000_0000_0000_0110_1010_1101_1000;
#50ns;
multiplier = 32'b0;
multiplicand = 32'b0;
$finish;
end
combinational_mult dut (product, multiplier, multiplicand);
endmodule
如果您有一個.sv文件擴展名而不是.v,大多數現代工具將解釋爲SystemVerilog。 – Morgan 2014-11-21 20:40:04