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我是新的使用vivado。我在FSM後合成時序仿真方面遇到了問題。模擬不能如何預測（行爲模擬和後綜合功能模擬工作）。 可能，約束存在一些問題（我使用約束嚮導來創建它們）。 時鐘頻率= 200赫茲。vivado約束問題與VHDL
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity control_asy_gate is
Port (clk : in STD_LOGIC;
rst_in : in STD_LOGIC;
full : in STD_LOGIC;
fine : in STD_LOGIC;
empty : in STD_LOGIC;
busy : in STD_LOGIC;
rst_out : out STD_LOGIC;
data_valid : out STD_LOGIC;
en_rom : out STD_LOGIC;
en_comp : out STD_LOGIC;
en_divisore : out STD_LOGIC;
en_trasm : out STD_LOGIC);
end control_asy_gate;
architecture Behavioral of control_asy_gate is
TYPE stati IS (init,trasmetti,compara,acquisizione,reset);
SIGNAL state: stati;
SIGNAL counter_rst: integer range 0 to 2:=0;
begin
en_divisore<= not fine;
comb: PROCESS (clk,rst_in, full, empty,state,busy)
begin
if rst_in='1' then
state<=init;
counter_rst<=0;
else
CASE state IS
WHEN init=>
if rising_edge(clk) then
state<= reset;
end if;
WHEN reset=>
if rising_edge(clk) then
if counter_rst=2 then
state<= trasmetti;
counter_rst<=0;
else
counter_rst<=counter_rst+1;
state<= reset;
end if;
end if;
WHEN trasmetti=>
if full='1' then
state<= compara;
else
state<= trasmetti;
end if;
WHEN compara=>
if empty='1' then
state<= acquisizione;
else
state<= compara;
end if;
WHEN acquisizione=>
if busy='1' then
state<=trasmetti;
else
state<=acquisizione;
end if;
end CASE;
end if;
end process;
PROCESS (state)
begin
CASE state IS
WHEN init=>
en_rom<='0';
rst_out<='0';
en_trasm<='0';
en_comp<='0';
data_valid<='0';
WHEN reset=>
rst_out<='1';
en_trasm<='0';
en_comp<='0';
en_rom<='0';
data_valid<='0';
WHEN trasmetti=>
en_rom<='1';
rst_out<='0';
en_trasm<='1';
en_comp<='0';
data_valid<='0';
WHEN compara=>
en_rom<='1';
rst_out<='0';
en_trasm<='0';
en_comp<='1';
data_valid<='0';
WHEN acquisizione=>
en_rom<='0';
rst_out<='0';
en_trasm<='0';
en_comp<='0';
data_valid<='1';
end CASE;
end process;
end Behavioral;
約束：
create_clock -period 5000000000.000 -name clk -waveform {0.0002500000000.000} [get_ports clk]
create_generated_clock -name {state_reg[0]__0_LDC_n_0} -source [get_pins{state_reg[0]__0_LDC/G}] -divide_by 1 [get_pins {state_reg[0]__0_LDC/Q}]
create_generated_clock -name {state_reg[0]__0_P_n_0} -source [get_ports clk] -divide_by 1 [get_pins {state_reg[0]__0_P/Q}]
create_generated_clock -name {state_reg[1]__0_P_n_0} -source [get_ports clk] -divide_by 1 [get_pins {state_reg[1]__0_P/Q}]
create_generated_clock -name {state_reg[2]__0_C_n_0} -source [get_ports clk] -divide_by 1 [get_pins {state_reg[2]__0_C/Q}]
create_generated_clock -name {state_reg__0[0]} -source [get_ports clk] -divide_by 1 [get_pins {state_reg[0]/Q}]
create_generated_clock -name {state_reg__0[2]} -source [get_ports clk] -divide_by 1 [get_pins {state_reg[2]/Q}]
set_input_delay -clock [get_clocks clk] -min -add_delay 1.210 [get_ports busy]
set_input_delay -clock [get_clocks clk] -max -add_delay 2.250 [get_ports busy]
set_input_delay -clock [get_clocks clk] -clock_fall -min -add_delay 1.210 [get_ports empty]
set_input_delay -clock [get_clocks clk] -clock_fall -max -add_delay 2.250 [get_ports empty]
set_input_delay -clock [get_clocks clk] -min -add_delay 1.210 [get_ports empty]
set_input_delay -clock [get_clocks clk] -max -add_delay 2.250 [get_ports empty]
set_input_delay -clock [get_clocks clk] -clock_fall -min -add_delay 1.210 [get_ports full]
set_input_delay -clock [get_clocks clk] -clock_fall -max -add_delay 2.250 [get_ports full]
set_input_delay -clock [get_clocks clk] -min -add_delay 1.210 [get_ports full]
set_input_delay -clock [get_clocks clk] -max -add_delay 2.250 [get_ports full]
set_input_delay -clock [get_clocks clk] -clock_fall -min -add_delay 1.210 [get_ports rst_in]
set_input_delay -clock [get_clocks clk] -clock_fall -max -add_delay 4.250 [get_ports rst_in]
set_input_delay -clock [get_clocks clk] -min -add_delay 1.210 [get_ports rst_in]
set_input_delay -clock [get_clocks clk] -max -add_delay 4.250 [get_ports rst_in]
create_clock -period 100.000 -name virtual_clock
set_input_delay -clock [get_clocks virtual_clock] -min -add_delay 1.000 [get_ports fine]
set_input_delay -clock [get_clocks virtual_clock] -max -add_delay 6.000 [get_ports fine]
set_output_delay -clock [get_clocks virtual_clock] -min -add_delay 8.000 [get_ports en_divisore]
set_output_delay -clock [get_clocks virtual_clock] -max -add_delay 15.000 [get_ports en_divisore]
你能幫我，我錯了理解，以及如何解決這個問題呢？
過程'梳子'混合順序和組合邏輯。首先，你應該檢查RTL而不是限制。 – ahmedus
請谷歌關於正確的同步過程語法在VHDL。網上有很多例子。例如你缺少'rising_edge（clk）'。還要檢查FPGA/ASIC工具製造商有關VHDL綜合指南的文檔 – JHBonarius