爲什麼VHDL不能移動工作？

Question

我是VHDL的新手，我正在嘗試寫一個左移位器，它需要一個32位值和一個5位值。左移位器然後試圖通過移出左邊的5位數字指定的位數並將右邊的多個零移出來來執行32位值的邏輯左移。我不明白爲什麼數組表示法不起作用。 1 < < 1的結果產生20000000而不是00000002.有人可以解釋我要去哪裏出錯嗎？下面的代碼：

SIGNAL lshiftOutput : STD_LOGIC_VECTOR(31 downto 0); 

COMPONENT Lshift32 
    Port(a : in STD_LOGIC_VECTOR(31 downto 0); 
      b : in STD_LOGIC_VECTOR(4 downto 0); 
      lshiftOutput : out STD_LOGIC_VECTOR(31 downto 0)); 
END COMPONENT; 

PROCESS( a, b, opcode, adderOutput, subtractOutput, xorOutput, lshiftOutput, rshiftOutput) 
BEGIN 
    IF opcode = "0000" THEN 
     result <= x"00000000"; 
    ELSIF opcode = "0001" THEN 
     result <= adderOutput; 
    ELSIF opcode = "0010" THEN 
     result <= subtractOutput; 
    ELSIF opcode = "0011" THEN 
     result <= NOT a; 
    ELSIF opcode = "0100" THEN 
     result <= a AND b; 
    ELSIF opcode = "0101" THEN 
     result <= a OR b; 
    ELSIF opcode = "0110" THEN 
     result <= xorOutput; 
    ELSIF opcode = "0111" THEN 
     result <= lshiftOutput; 
    ELSIF opcode = "1000" THEN 
     result <= rshiftOutput; 
    END IF; 
END PROCESS; 

LIBRARY ieee; 
USE ieee.std_logic_unsigned.ALL; 
USE ieee.std_logic_1164.ALL; 
USE ieee.numeric_std.ALL; 


ENTITY Lshift32 IS 
    Port(a : in STD_LOGIC_VECTOR (31 downto 0); 
      b : in STD_LOGIC_VECTOR (4 downto 0); 
      lshiftOutput : out STD_LOGIC_VECTOR (31 downto 0)); 
END Lshift32; 

ARCHITECTURE Lshift32Architecture of Lshift32 IS 
BEGIN 
    PROCESS(a, b) 
    VARIABLE shiftAmount : INTEGER := 0; 
    BEGIN 
     shiftAmount := to_integer(b(4 downto 0)); 
     -- Shift left 
     lshiftOutput <= a(31-shiftAmount downto 0) & (shiftAmount-1 downto 0 => '0'); 
    END PROCESS; 
END Lshift32Architecture; 

該試驗檯是這樣的：

-- Shift Left ------------------------------------------------------- 
WAIT FOR 9 ns; 
op <= "0111"; 
-- 1 << 1 
input_a <= x"00000001"; 
input_b <= x"00000001"; 
WAIT FOR 1 ns; 
IF (output /= x"00000002") THEN 
    ASSERT false REPORT "1 << 1 has incorrect result" severity error; 
END IF; 

Answer 1

布賴恩問你提供的一個Minimal, Complete, and Verifiable example，您編輯的代碼沒有做到這一點。而對於要求的原因是，它可以創建一個圍繞您最初提供的代碼部分的MCVE，它得到正確的答案：

library ieee; -- added 
use ieee.std_logic_1164.all; -- added 
use ieee.numeric_std_unsigned.all; -- added 

entity lshift32 is 
    port(a : in std_logic_vector (31 downto 0); 
      b : in std_logic_vector (4 downto 0); 
      lshiftoutput : out std_logic_vector (31 downto 0)); 
end entity lshift32; 

architecture lshift32architecture of lshift32 is 
begin 
    process(a, b) 
    variable shiftamount : integer := 0; 
    begin 
     shiftamount := to_integer(b(4 downto 0)); 
     -- shift left 

     lshiftoutput <= a(31-shiftamount downto 0) & (shiftamount-1 downto 0 => '0'); 
    end process; 
end architecture lshift32architecture; 

library ieee; 
use ieee.std_logic_1164.all; 
use ieee.numeric_std_unsigned.all; 

entity lshift32_tb is 
end entity; 

architecture foo of lshift32_tb is 
    signal a: std_logic_vector (31 downto 0) := (others => '0'); 
    signal b: std_logic_vector (4 downto 0) := (others => '0'); 
    signal lshiftoutput: std_logic_vector (31 downto 0); 
begin 

DUT: 
    entity work.lshift32 
     port map (
      a => a, 
      b => b, 
      lshiftoutput => lshiftoutput 
     ); 

SIMULIS: 
    process 
    begin 
     wait for 10 ns; 
     a(0) <= '1'; -- 1 
     b(0) <= '1'; -- 1 
     wait for 10 ns; 
     wait; 
    end process; 

ANALYSIS: 
    process (lshiftoutput) 
    variable shiftamount: integer; 
    begin 
     if now > 0 ns then 
      shiftamount := to_integer(b); 
      report "ShiftAmount = " & integer'image(shiftamount); 
      report "lshiftOutput = " & to_string(lshiftoutput); 
     end if; 
    end process; 
end architecture; 

並運行上述測試平臺提供了：

ghdl -a --std = 08 lshift.vhdl
ghdl -e --std = 08 lshift32_tb
ghdl -r lshift32_tb
lshift.vhdl：60：13：@ 10ns的：（報告注）：ShiftAmount = 1
lshift.vhdl：61：13：@ 10ns：（report n注意：lshiftOutput = 00000000000000000000000000000010

而且你的執行失敗說你的測試平臺的上下文子句（使用子句）或有問題。

請注意，您正在使用none標準軟件包std_logic_unsigned和IEEE標準軟件包numeric_std。你真的不應該混搭，可能會有意想不到的後果。

軟件包numeric_std_unsigned可用於符合IEEE Std 1076-2008標準的VHDL實現。如果使用先前版本的VHDL標準，則可以使用軟件包numeric_std並鍵入convert b以作爲傳遞到to_integer的表達式的無符號數。

對於隨此答案提供的測試臺，您還會發現未提供針對std_logic_vector的to_string。沒有看到你的整個測試平臺，它很可能是功能性的。

如果你想證明的答案提供測試平臺的作品在非-2008修訂環境：

function to_string (inp: std_logic_vector) return string is 
    variable image_str: string (1 to inp'length); 
    alias input_str: std_logic_vector (1 to inp'length) is inp; 
begin 
    for i in input_str'range loop 
     image_str(i) := character'VALUE(std_ulogic'IMAGE(input_str(i))); 
    end loop; 
    return image_str; 
end function; 

功能可以提供作爲架構聲明項。