2012-10-31 64 views
1

我嘗試編寫K.I.T.T的VHDL代碼。掃描儀對FPGA LED,但是我需要更改此代碼:VHDL K.I.T.T.掃描儀

with state select 
      led1 <= '1' when forward1, 
       '0' when others; 

    with state select 
     led2 <= '1' when forward2, 
      '0' when others; 

    with state select 
     led3 <= '1' when forward3, 
      '0' when others; 

    with state select 
     led4 <= '1' when forward4, 
      '0' when others; 

with state select 
        led1,led2,led3 <= '1' when forward1, 
         '0' when others; 
     with state select 
        led2, led3,led4 <= '1' when forward2, 
        '0' when others; 
with state select 
        led3, led4,led5 <= '1' when forward2, 
        '0' when others; 

但是當我這樣做,我收到錯誤 - 預期「(」或其他 我怎樣才能改變這個代碼改變乘法輸出

回答

2

你可以這樣做:?

led_select : process(state) 
begin 
    case state is 
    when forward1 => 
    led_states <= "00111"; 
    when forward2 => 
    led_states <= "01110"; 
    when forward3 => 
    led_states <= "11100"; 
    when others => 
    led_states <= (others => '0'); 
    end case; 
end process; 

led1 <= led_states(0); 
led2 <= led_states(1); 
led3 <= led_states(2); 
led4 <= led_states(3); 
led5 <= led_states(4); 

在哪裏led_states是一個信號,聲明爲signal led_states : std_logic_vector(4 downto 0);