依賴於輸入事件的狀態轉換VHDL

Question

我是VHDL的新手。我目前正在開發一個FSM，我希望我的狀態機只有在我的輸入發生變化時才改變狀態。我應該在下面的代碼中做出什麼改變？

entity fsm is 
    Port (clk : in STD_LOGIC; 
      reset : in STD_LOGIC; 
      x_in : in STD_LOGIC;       -- input Bitstream 
      y_out : out STD_LOGIC_VECTOR (1 downto 0)); -- Encoded output 
end fsm; 

----------------------------------------------------- 
architecture Behavioral of fsm is 

    -- Building an Enumerated type for the state machine 
    type state_type is (s_idle,s1,s2,s3,s4); -- constraint length = 3, Hence number of Regs = 2 therefore Number of states = 4 
    signal state, next_state: state_type ; -- Registers to hold the Present and next states 

begin 
----------------------------------------------------- 
    process1: process (reset, clk)    -- Sequential Logic Selection process: 
    begin 

      if (reset ='1') then 
       state <=s_idle;   
      elsif (clk='1' and x_in'Event) then  
       state <= next_state; 
      end if; 
-----------------------------------------------------   
    end process process1; 

Answer 1

假設你想使FSM改變狀態時 - >

1. 的clk高
2. 的X_in值更改

另外，我會假設你的next_state變量是你沒有提到的state的組合函數。只需進行一次更改即可，將X_in添加到您的過程敏感性列表中。

----------------------------------------------------- 
    process1: process (X_in, reset, clk)    -- Sequential Logic Selection process: 
    begin 

      if (reset ='1') then 
       state <=s_idle;   
      elsif (clk='1' and x_in'Event) then  
       state <= next_state; 
      end if; 
-----------------------------------------------------   
    end process process1; 

Answer 2

假設x_in輸入同步到clk，這會做你的描述：

process1: process (reset, clk) 
begin 

     if (reset ='1') then 
      state <=s_idle;   
     elsif (clk='1' and clk'Event) then 
      x_in_prev <= x_in; 
      if x_in_prev /= x_in then 
       state <= next_state; 
      end if; 
     end if; 
end process process1; 

你需要在你的架構定義x_in_prev信號，這個編譯。