2016-06-08 92 views
0

我正試圖學習如何從命令行生成位文件。有沒有辦法從命令行工具生成.xst腳本文件?我只能發現它是GUI自動生成的東西。如何從命令行生成.xst文件+ Xilinx-ISE

要添加一些上下文,我在GUI中構建並生成一個簡單設計的位文件,然後使用'查看命令行日誌'工具生成該工具使用的命令。然後使用「清理項目文件」。我只是試圖從命令行手動執行相同的命令。第一個命令是:

xst -ifn "C:/Users/Documents/XilinxProjects/SingleItemTest/item.xst" -ofn "C:/Users/Documents/XilinxProjects/SingleItemTest/item.syr" 

這給了我:

ERROR:Xst:427 - Entry File C:/Users/Documents/XilinxProjects/SingleItemTest/item.xst not found 

回答

0

我們PoC-Library可以從命令行通過Python3運行賽靈思XST。我們使用XST的模板文件,因爲每個目標設備都可以有其他XST選項。

這裏是7系列XST一個* .xst文件運行:

set -xsthdpdir "xst" 
run 
-ifn {prjFile} 
-use_new_parser {UseNewParser} 
-ifmt {InputFormat} 
-ofn {OutputName} 
-ofmt {OutputFormat} 
-p {Part} 
-top {TopModuleName} 
-opt_mode {OptimizationMode} 
-opt_level {OptimizationLevel} 
-power {PowerReduction} 
-iuc {IgnoreSynthesisConstraintsFile} 
-uc {SynthesisConstraintsFile} 
-keep_hierarchy {KeepHierarchy} 
-netlist_hierarchy {NetListHierarchy} 
-rtlview {GenerateRTLView} 
-glob_opt {GlobalOptimization} 
-read_cores {ReadCores} 
-sd {SearchDirectories} 
-write_timing_constraints {WriteTimingConstraints} 
-cross_clock_analysis {CrossClockAnalysis} 
-hierarchy_separator {HierarchySeparator} 
-bus_delimiter {BusDelimiter} 
-case {Case} 
-slice_utilization_ratio {SliceUtilizationRatio} 
-bram_utilization_ratio {BRAMUtilizationRatio} 
-dsp_utilization_ratio {DSPUtilizationRatio} 
-lc {LUTCombining} 
-reduce_control_sets {ReduceControlSets} 
-fsm_extract {FSMExtract} 
-fsm_encoding {FSMEncoding} 
-safe_implementation {FSMSafeImplementation} 
-fsm_style {FSMStyle} 
-ram_extract {RAMExtract} 
-ram_style {RAMStyle} 
-rom_extract {ROMExtract} 
-shreg_extract {ShRegExtract} 
-rom_style {ROMStyle} 
-auto_bram_packing {AutoBRAMPacking} 
-resource_sharing {ResourceSharing} 
-async_to_sync {ASyncToSync} 
-use_dsp48 {UseDSP48} 
-iobuf {IOBuf} 
-max_fanout {MaxFanOut} 
-bufg {BufG} 
-register_duplication {RegisterDuplication} 
-register_balancing {RegisterBalancing} 
-optimize_primitives {OptimizePrimitives} 
-use_clock_enable {UseClockEnable} 
-use_sync_set {UseSyncSet} 
-use_sync_reset {UseSyncReset} 
-iob {PackIORegistersIntoIOBs} 
-equivalent_register_removal {EquivalentRegisterRemoval} 
-slice_utilization_ratio_maxmargin {SliceUtilizationRatioMaxMargin} 

來源:https://github.com/VLSI-EDA/PoC/tree/master/xst