VHDL - BCD轉換爲二進制輸入緩衝區 - 顯示結果的問題

Question

我正在使用Vivado 2014.2將BCD的VHDL代碼寫入可用於計算器或組合鎖的二進制輸入緩衝區。

我的方法很簡單。做x * 10它與x（2 + 8）= x * 2 + x * 8相同。

X * 2 = 1個左移（2^1 = 2）

X * 8 = 3左

輸出緩衝器（tempC）被移位，並加入移位（2^3 = 8）在添加輸入之前。這樣做是爲了當從空開始，以便輸入的第一個數字不會出來乘以10.

我的代碼編譯並運行在artix 7 fpga上，但我遇到問題確保輸出緩衝區（tempC）工作正常。它拒絕輸出任何數據，但我不知道爲什麼。

我可能會將這些值加在一起錯誤，但我不認爲它是這樣的。也許我正在鑄造一個錯誤的數據類型？

任何幫助，非常感謝。

-- Engineer: greatgamer34 
-- 
-- Create Date: 01/25/2017 04:57:02 PM 
-- Design Name: 
-- Module Name: buff - Behavioral 


library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 

use ieee.numeric_std.all; 

entity buff is 
Port (Data : in STD_LOGIC_VECTOR (3 downto 0); ----4bit BCD value input 
     Clock : in STD_LOGIC; 
     Reset : in STD_LOGIC; 
     Output : out STD_LOGIC_VECTOR (15 downto 0); 
     aout : out STD_LOGIC_VECTOR (6 downto 0));-- 7 segment display output    for current state. 
end buff; 

architecture Behavioral of buff is 
type states is (state0, state1, state2, state3); 
signal currentstate, nextstate: states; 
signal tempA: STD_LOGIC_VECTOR (15 downto 0);---used to store 'Data' for addition. 
signal tempB: STD_LOGIC_VECTOR (15 downto 0);---used for x2('Data'). 
signal tempC: STD_LOGIC_VECTOR (15 downto 0);---used as output register. 
signal tempD: STD_LOGIC_VECTOR (15 downto 0);---used for sending data to LED's. 
signal tempE: STD_LOGIC_VECTOR (15 downto 0);---used for x8('Data') 
begin 
Process(Reset,clock) 
Begin 
if(Reset = '1') then 
    tempC <= "0000000000000000"; --clear tempC 
    tempA <= "0000000000000000"; --clear tempA 
    currentstate <= state0; -------reset state to 0 
elsif(clock'event and clock = '1') then 
    output <= (tempD);--dispaly the output of the buffer 
     currentstate<=nextstate; -- advance states 
end if; 

end process; 

process(currentstate) 
begin 
case currentstate is 

when state0 => 
    tempA(3 downto 0) <= Data; -- load in 4 bit data intoi 16 bit register 
    tempD <= (tempA); --output the input data(used for debugging) 
    nextstate <= state1; 
    aout <= not "1111110"; -- output on the 7 seg the number 0 


when state1 => 
    tempB <= tempC(14 downto 0) & '0'; --left shift tempC(the output  register) save to tempB; this is the x2 multiplication 
    tempD <= (tempA); -- output the input data(used for debugging) 
    nextstate <= state2; 
    aout <= not "0110000"; -- output on the 7 seg the number 1 

when state2 => 
    tempE <= tempC(12 downto 0) & "000"; --left shift tempC(the output  register) three times save to tempE; this is the x8 multiplication 
    --tempC <=std_logic_vector(unsigned(tempE) + unsigned(tempD)); (TESTING) 
    tempC <=std_logic_vector(('0' & unsigned(tempE(14 downto 0))) + ('0' & unsigned(tempD(14 downto 0)))); --add the first 15 bits of tempD and tempE(this  is how we multiply by 10) 
    tempD <= (tempC); -- output the x10 output register 
    nextstate <= state3; 
    aout <= not "1101101" ; -- output on the 7 seg the number2 

when state3 => 
    -- tempC <= ('0' & tempC(14 downto 0)) + ('0' & tempA(14 downto 0)); (TESTING) 
    tempC <= std_logic_vector(('0' & unsigned(tempC(14 downto 0))) + ('0' & unsigned(tempA(14 downto 0)))); --add the 'Data' to the x10 shifted number. 
    tempD <= (tempC); 
    nextstate <= state0; 
    aout <= not "1111001"; -- output on the 7 seg the number3 
end case; 
end process; 
end behavioral; 

Answer 1

好的，在一些評論和答案的幫助下，我能夠得到它的工作。以下是使用的代碼。

library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 

use ieee.numeric_std.all; 

entity buff is 
Port (Data : in STD_LOGIC_VECTOR (3 downto 0); ----4bit BCD value input 
     Clock : in STD_LOGIC; 
     Reset : in STD_LOGIC; 
     Output : out STD_LOGIC_VECTOR (15 downto 0); 
     aout : out STD_LOGIC_VECTOR (6 downto 0));-- 7 segment display output for current state. 
end buff; 

architecture Behavioral of buff is 
type states is (state0, state1, state2, state3, state4); 
signal currentstate, nextstate: states; 
signal tempA: STD_LOGIC_VECTOR (3 downto 0);---used to store 'Data' for addition. 
signal tempB: STD_LOGIC_VECTOR (15 downto 0);---used for x2('Data'). 
signal tempC: STD_LOGIC_VECTOR (15 downto 0);---used as output register. 
signal tempD: STD_LOGIC_VECTOR (15 downto 0);---used for sending data to LED's. 
signal tempE: STD_LOGIC_VECTOR (15 downto 0);---used for x8('Data') 
signal tempF: STD_LOGIC_VECTOR (15 downto 0); 
begin 
Process(Reset,clock) 
Begin 
if(Reset = '1') then 
    currentstate <= state4; 
    Output <= "0000000000000000"; -------reset state 
elsif(clock'event and clock = '1') then 
     Output <= tempD ;--display the output of the buffer 
     currentstate <= nextstate; -- advance states 
end if; 

end process; 

process(currentstate) 
begin 
case currentstate is 

when state0 => 
    tempA <= Data; -- load in 4 bit data intoi 16 bit register 
    tempD(3 downto 0) <= tempA; --output the input data(used for debugging) 
    nextstate <= state1; 
    aout <= not "1111110"; -- output on the 7 seg the number 0 


when state1 => 
    tempB <= (tempC(14 downto 0) & "0"); --left shift tempC(the output register) save to tempB; this is the x2 multiplication 
    tempD <= (tempB); -- output the input data(used for debugging) 
    nextstate <= state2; 
    aout <= not "0110000"; -- output on the 7 seg the number 1 

when state2 => 
    tempE <= tempC(12 downto 0) & "000"; --left shift tempC(the output register) three times save to tempE; this is the x8 multiplication 
    --tempF <=std_logic_vector(unsigned(tempE) + unsigned(tempB)); --(TESTING) 
    tempF <=std_logic_vector(('0' & unsigned(tempE(14 downto 0))) + ('0' & unsigned(tempB(14 downto 0)))); --add the first 15 bits of tempD and tempE(this is how we multiply by 10) 
    tempD <= tempE; -- output the x10 output register 
    nextstate <= state3; 
    aout <= not "1101101" ; -- output on the 7 seg the number2 

when state3 => 
    --tempC <=std_logic_vector(unsigned(tempC) + unsigned(tempA)); 
    tempC <= std_logic_vector(('0' & unsigned(tempF(14 downto 0))) + ("000000000000" & unsigned(tempA))); --add the 'Data' to the x10 shifted number. 
    tempD <= tempC; 
    nextstate <= state0; 
    aout <= not "1111001"; -- output on the 7 seg the number3 

    when state4 => 
    tempC <= "0000000000000000"; 
    tempA <= "0000"; 
    tempB <= "0000000000000000"; 
    tempD <= "0000000000000000"; 
    tempE <= "0000000000000000"; 
    tempF <= "0000000000000000"; 
    nextstate <= state0; 
    aout <= not "0110011"; 

    end case; 
end process; 
end behavioral; 

Answer 2

答：

tempC是在計時過程中復位，然後獲得在組合過程中分配新值。 不允許在兩個不同的進程中爲信號賦值。組合過程的靈敏度列表也是丟失的信號。

觀察：

1. 使用你的信號tempX非常混亂邏輯名稱。我也無法想象你的BCD電路將被稱爲BUFF;）
2. 檢查組合過程的靈敏度列表。
3. 谷歌上的狀態機需要如何構建
4. 仿真您的設計中非常重要的（特別是對於較大的設計） 看看不同的在線教程如Xilinx Vivado 2015.2 Simulation Tutorial

快樂調試