1
我想在vhdl中爲我的心跳傳感器做一個計數器。我有一個傳感器在每次心臟跳動時點亮,我想要統計點亮了多少次,但代碼缺少一些節拍。心率傳感器的Vhdl計數器
我的代碼
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity pulse is port(
heartin : in std_logic;
clk : in std_logic;
reset : in std_logic;
F : out std_logic_vector (6 downto 0)
);
end pulse;
architecture Behavioral of pulse is
component clkdivider is Port (
clkin: in std_logic;
clkout:out std_logic
);
end component;
signal x : std_logic_vector (3 downto 0):= "0000";
signal y : std_logic_vector (6 downto 0);
signal wire: std_logic;
begin
L2:clkdivider port map (clkin=>clk, clkout=>wire);
process(wire)
begin
if rising_edge (wire) then
if reset = '1' then
x <= "0000";
elsif heartin = '1' then
x <= (x + "0001");
end if;
end if;
end process;
process(x,y)
begin
case x is
when "0000"=> y<="1000000"; -- '0'
when "0001"=> y<="1111001"; -- '1'
when "0010"=> y<="0100100"; -- '2'
when "0011"=> y<="0110000"; -- '3'
when "0100"=> y<="0011001"; -- '4'
when "0101"=> y<="0010010"; -- '5'
when "0110"=> y<="0000010"; -- '6'
when "0111"=> y<="1111000"; -- '7'
when "1000"=> y<="0000000"; -- '8'
when "1001"=> y<="0010000"; -- '9'
when "1010"=> y<="0001000"; -- 'A'
when "1011"=> y<="0000011"; -- 'b'
when "1100"=> y<="1000110"; -- 'C'
when "1101"=> y<="0100001"; -- 'd'
when "1110"=> y<="0000110"; -- 'E'
when others=> y<="0001110"; -- 'F'
end case;
end process;
F <= y;
end Behavioral;
Clkdivider代碼:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity clkdivider is Port (
clkin: in std_logic;
clkout:out std_logic
);
end clkdivider;
architecture Behavioral of clkdivider is
signal int_clock:std_logic;
begin
clkout<=int_clock;
process(clkin)
variable var:integer range 0 to 2200000 :=0;
begin
if (clkin'event and clkin = '1') then
if var = 2200000 then
int_clock <= not int_clock;
var := 0;
else
var := var+1;
end if;
end if;
end process;
end Behavioral;
請整理你的代碼縮進,以便我們更容易閱讀。 –