VHDL計數器錯誤

Question

我已經完成了代碼，它可以工作，但是當我嘗試寫測試平臺時，我遇到了一些麻煩。輸入x設置爲8位，x：IN BIT_VECTOR（N -1 DOWNTO 0）。 當我編寫測試臺時，我不輸入位數。

library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 
USE ieee.std_logic_unsigned.all; 

ENTITY Count_ones IS 
    GENERIC (N: INTEGER := 8); -- number of bits 
    PORT (x: IN BIT_VECTOR (N -1 DOWNTO 0); y: OUT NATURAL RANGE 0 TO N); 
END ENTITY ; 

architecture Behavioral of Count_ones is 
    TYPE count is Array (N DOWNTO 1) OF Natural; 
    signal a : count; 

begin 

    a(0) <= 1 when (x(0) = '1') 
    else 
     0; 
    gen: FOR i IN N-1 DOWNTO 0 
    GENERATE 
      a(i+1) <= (a(i)+1) when (x(i)='0') 
      else 
        a(i); 
END GENERATE; 

y <= a(N-1); 

end Behavioral; 

試驗檯：

LIBRARY ieee; 
USE ieee.std_logic_1164.ALL; 
USE ieee.std_logic_unsigned.all; 

ENTITY Count_ones_TB IS 
END Count_ones_TB; 

ARCHITECTURE behavior OF Count_ones_TB IS 


COMPONENT Count_ones 
PORT(
    x : IN std_logic_vector(7 downto 0); 
    y : OUT std_logic_vector(0 to 3) 
    ); 
END COMPONENT; 

--Inputs 
signal x : std_logic_vector(7 downto 0) := (others => '0'); 

--Outputs 
signal y : std_logic_vector(0 to 3); 


BEGIN 

-- Instantiate the Unit Under Test (UUT) 
uut: Count_ones PORT MAP (
     x => x, 
     y => y 
    ); 

stim_proc: process 
begin  

     x <= "00010101"; 
     wait for 100 ns;  
     x <= "00001001"; 
     wait for 100 ns; 
     x <= "11111111101" 
     wait for 100ns; 
    -- insert stimulus here 

    wait; 
end process; 

END; 

該錯誤是

實體端口x不與組件端口 實體端口Y的類型std_logic_vector匹配不與部件端口的類型std_logic_vector匹配

請幫助我，我真的不知道如何解決這個問題。

Answer 1

您的具體問題的答案是實體中的端口類型，組件中的端口和信號類型必須匹配。以下是您的代碼的link，這些錯誤以及更多更正。

library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 
USE ieee.std_logic_unsigned.all; 

ENTITY Count_ones IS 
    GENERIC (N: INTEGER := 8); -- number of bits 
    PORT (x: IN BIT_VECTOR (N -1 DOWNTO 0); y: OUT NATURAL RANGE 0 TO N); 
END ENTITY ; 

architecture Behavioral of Count_ones is 
    TYPE count is Array (N DOWNTO 0) OF Natural; 
    signal a : count; 

begin 

    a(0) <= 1 when (x(0) = '1') 
    else 
     0; 
    gen: FOR i IN N-1 DOWNTO 0 
    GENERATE 
      a(i+1) <= (a(i)+1) when (x(i)='0') 
      else 
        a(i); 
END GENERATE; 

y <= a(N-1); 

end Behavioral; 

LIBRARY ieee; 
USE ieee.std_logic_1164.ALL; 
USE ieee.std_logic_unsigned.all; 

ENTITY Count_ones_TB IS 
END Count_ones_TB; 

ARCHITECTURE behavior OF Count_ones_TB IS 


COMPONENT Count_ones 
    GENERIC (N: INTEGER := 8); -- number of bits 
    PORT (x: IN BIT_VECTOR (N -1 DOWNTO 0); 
      y: OUT NATURAL RANGE 0 TO N); 
END COMPONENT; 

--Inputs 
signal x : BIT_VECTOR(7 downto 0) := (others => '0'); 

--Outputs 
signal y : natural; 


BEGIN 

-- Instantiate the Unit Under Test (UUT) 
uut: Count_ones PORT MAP (
     x => x, 
     y => y 
    ); 

stim_proc: process 
begin  

     x <= "00010101"; 
     wait for 100 ns;  
     x <= "00001001"; 
     wait for 100 ns; 
     x <= "11111101"; 
     wait for 100ns; 
    -- insert stimulus here 

    wait; 
end process; 

END; 

但是我必須指出，要實現你的目標，試圖計算一個數目，你還有很長的路要走。

正因爲如此：

1. 我更正你的代碼並不是唯一正確的答案。在 事實上，我的更正甚至不是一個好的答案。我只是簡單地將 作爲最小更正，以使您的代碼編譯和運行。您需要 非常仔細地考慮您的 設計中所有端口和信號的類型。
2. 我的更正將不會使您的代碼正常工作，即計算出 的數量。