類型錯誤綴表達式VHDL

Question

我編碼在VHDL鹼性組合電路，其具有帶有兩個輸入端a和b的AND門。該「t」的輸出與否定輸入「c」進行或運算。然後這個輸出「s」與NAND同「a」一起給出最終輸出「d」。

這是代碼。

library ieee; 
use ieee.std_logic_1164.all; 
entity logicgate is 
port(a,b,c: in std_logic; 
d: out std_logic); 
end logicgate; 

architecture arch_logicgate of logicgate is 
begin 
signal s: std_logic; 
signal t: std_logic; 
t<= a and b; 
s<= (not c) or t; 
d<= a nand s; 
end arch_logicgate; 

成績單：

-- Compiling architecture arch_logicgate of logicgate 
# ** Error: C:/Modeltech_pe_edu_10.1d/examples/logicgate.vhdl(12): near "signal": syntax error 
# ** Error: C:/Modeltech_pe_edu_10.1d/examples/logicgate.vhdl(14): (vcom-1136) Unknown identifier "s". 
# 
# ** Error: C:/Modeltech_pe_edu_10.1d/examples/logicgate.vhdl(14): Type error resolving infix expression "nand" as type ieee.std_logic_1164.STD_LOGIC. 
# ** Error: C:/Modeltech_pe_edu_10.1d/examples/logicgate.vhdl(15): VHDL Compiler exiting 

我知道我錯過了基礎。請幫助我。

Answer 1

第一錯誤消息：

** Error: C:/Modeltech_pe_edu_10.1d/examples/logicgate.vhdl(12): near "signal": syntax error 

的產生是因爲有在執行區中的聲明。

把他們在聲明區，前begin

architecture arch_logicgate of logicgate is 
    signal s: std_logic; 
begin 
    ...