2014-03-04 76 views
0

我只能使用四個7段顯示中的一個。如果我評論這行代碼led ledh(rn1_temp[7:4], segh_temp);,它會運行良好,即使有一些警告消息。但是當我嘗試使用其中的兩個顯示5位數字時,它給了我這兩個錯誤。在7段顯示隨機生成的數字

ERROR:MapLib:979 - LUT2 symbol "seg<2>1" (output signal=seg_2_OBUF) has input 
signal "seg_5_OBUF" which will be trimmed. See Section 5 of the Map Report 
File for details about why the input signal will become undriven. 
ERROR:MapLib:978 - LUT2 symbol "seg<2>1" (output signal=seg_2_OBUF) has an 
equation that uses input pin I0, which no longer has a connected signal. 
Please ensure that all the pins used in the equation for this LUT have 
signals that are not trimmed (see Section 5 of the Map Report File for 
details on which signals were trimmed). 

我需要一些慢時鐘嗎?我不知道這個代碼有什麼問題。 任何援助將不勝感激。

module fivebit_RandomNumber (rst, clk, rn);//generate a 5-bit random number 
input rst, clk; 
output reg [4:0] rn; 

wire w14; 
assign w14 = rn[1]^rn[4]; 


always @ (posedge clk) 
if (~rst) 
    begin 
     rn <= 5'b11111; 
end else 
    begin 
     rn <= {rn[3],rn[2],rn[1],rn[0],w14}; 
    end 

endmodule 



module led(rn, seg); 

input [3:0] rn; 
output [7:0] seg; 


reg [7:0] seg_temp; 
always @ (*) 
begin 
case (rn) 
    4'b0000 : seg_temp = 8'b00000011; 
    4'b0001 : seg_temp = 8'b10011111;  //1 
    4'b0010 : seg_temp = 8'b00100101;  //2 
    4'b0011 : seg_temp = 8'b00001101;  //3 
    4'b0100 : seg_temp = 8'b10011001;  //4 
    4'b0101 : seg_temp = 8'b01001001;  //5 
    4'b0110 : seg_temp = 8'b01000001;  //6 
    4'b0111 : seg_temp = 8'b00011111;  //7 
    4'b1000 : seg_temp = 8'b00000001;  //8 
    4'b1001 : seg_temp = 8'b00011001;  //9 
    4'b1010 : seg_temp = 8'b00010001;  //10 
    4'b1011 : seg_temp = 8'b11000001;  //11 
    4'b1100 : seg_temp = 8'b01100011;  //12 
    4'b1101 : seg_temp = 8'b10000101;  //13 
    4'b1110 : seg_temp = 8'b01100001;  //14 
    4'b1111 : seg_temp = 8'b01110001;  //15 
    default : seg_temp = 8'b11111111; 
endcase 
end 

assign seg = seg_temp; 

endmodule 


module display(clk, rst, btn, seg, anodes); 

input clk, btn, rst; 


output [7:0] seg; 
output [3:0] anodes; 


wire [4:0] imrn; 

fivebit_RandomNumber frn (rst, clk, imrn); 

reg enable; 

always @ (posedge clk or negedge btn) 
begin 
if (~btn) 
begin 
    enable = 1; 
end 
else 
begin 
    enable = 0; 
end 
end 

reg [7:0] rn1_temp; 

always @ (*) 
begin 
if (enable) 
begin 
    rn1_temp = {0,0,0,imrn}; 
end 
end 


reg [3:0] anodes; 

wire [7:0] segl_temp, segh_temp; 
reg [7:0] seg_temp; 


led ledh(rn1_temp[7:4], segh_temp);  //a problem in this line 
led ledl(rn1_temp[3:0], segl_temp); 

always @ (*) 
begin 
case (anodes) 
    4'b1111 : anodes = 4'b1101; 
    4'b1101 : anodes = 4'b1110; 
    4'b1110 : anodes = 4'b1101; 
    default : anodes = 4'b1111; 
endcase 
case (anodes) 
    4'b1101 : seg_temp = segh_temp; 
    4'b1110 : seg_temp = segl_temp; 
    default : seg_temp = 8'b11111111; 
endcase 
end 

assign seg = (&anodes) ? 8'b11111111 : seg_temp; 


endmodule 
+0

問題出在驅動'anodes'和'seg_temp'的最後'always @ *'。由於'anodes'由'anodes'決定,它推斷複雜的鎖存邏輯,如果它甚至可以合成。目前還不清楚你打算如何分享一個展示。因此,只要有更新到'rn1_temp','anodes'就會改變,只會更新一個顯示,而不管值更改爲'rn1_temp'。請詳細說明你的意圖。 – Greg

+0

是的,謝謝你的觀點。我試圖複用顯示器。我改變了這個代碼塊,在一個'counter'上添加了case語句,就像一個慢時鐘,而不是直接在'anodes'上。再次感謝。我只是verilog的新手,所以需要時間去適應它。 – n00d1es

回答

0

看起來像你試圖複用seg輸出。嘗試改變下列:

output [7:0] seg; 
output [3:0] anodes; 

// ... 
reg [3:0] anodes; 
/// ... 
reg [7:0] seg_temp; 
/// ... 

always @ (*) 
begin 
case (anodes) 
    4'b1111 : anodes = 4'b1101; 
    4'b1101 : anodes = 4'b1110; 
    4'b1110 : anodes = 4'b1101; 
    default : anodes = 4'b1111; 
endcase 
case (anodes) 
    4'b1101 : seg_temp = segh_temp; 
    4'b1110 : seg_temp = segl_temp; 
    default : seg_temp = 8'b11111111; 
endcase 
end 

assign seg = (&anodes) ? 8'b11111111 : seg_temp; 

到:

output reg [7:0] seg; 
output reg [3:0] anodes; 

// ... 

always @ (posedge clk) 
begin 
case (anodes) 
    4'b1111 : anodes <= 4'b1101; 
    4'b1101 : anodes <= 4'b1110; 
    4'b1110 : anodes <= 4'b1101; 
    default : anodes <= 4'b1111; 
endcase 
end 

always @ (*) 
begin 
case (anodes) 
    4'b1101 : seg = segh_temp; 
    4'b1110 : seg = segl_temp; 
    default : seg = 8'b11111111; 
endcase 
end 

這樣anodes被同步由clkseg控制仍的組合邏輯。

同步分配應使用非阻塞(<=)。將您的作業更新爲enable以實現無阻塞。