我是Verilog的新手,我正在嘗試創建一個我的第一個程序,它應該在keybord上的鍵被按下時顯示某些內容。我想使用Verilog教程中的示例代碼,但是我在引腳分配方面存在一些問題(我使用Altera的DE2-70)。Verilog中的Keybord接口設計
- 爲什麼我有
input ReadKB;
而在模塊定義中沒有這樣的東西? - 我知道哪些引腳應該分配給KBclk和KBdata。 ?(
PS2_KBCLK PIN_F24 PS/2 Clock
和(PS2_KBDAT PIN_E24 PS/2 Data
)怎麼樣ResetKB
在泛讀教材,沒有解釋,我真的courious它
代碼:!
module KeyboardInterface(KBclk, KBdata, ResetKB, SYNclk, ScanRdy, ScanCode, KeyReleased);
input KBclk;
input KBdata;
input ResetKB;
input ReadKB;
input SYNclk;
output ScanRdy;
output ScanCode;
output KeyReleased;
//Generate an internal synchronized clock
reg Clock;
always @(posedge SYNclk) Clock = KBclk;
reg[3:0] BitCount;
reg StartBitDetected, ScanRdy;
reg[7:0] ScanCode;
//Count the number of serial bits and collect data into ScanCode
always @(posedge Clock) begin
if(ResetKB) begin
BitCount=0; StartBitDetected =0;
end else begin
if(KBdata == 0 && StartBitDetected == 0) begin
StartBitDetected=1;
ScanRdy = 0;
end else if (StartBitDetected) begin
if(BitCount < 8) begin
BitCount = BitCount + 1;
ScanCode = {KBdata, ScanCode[7:1]};
end else begin
StartBitDetected = 0;
BitCount = 0;
ScanRdy = 1;
end
end
end
end
reg [1:0] CompletionState;
wire KeyReleased;
//keep track of the state of Scan Codes outputted
always @(posedge SYNclk) begin
if(ResetKB) CompletionState = 0;
else case(CompletionState)
0: if(ScanCode == 8'h70 && ScanRdy == 1) CompletionState =1;
else CompletionState =0;
1: if(ScanRdy == 1) CompletionState =1;
else CompletionState =2;
2: if(ScanRdy == 0) CompletionState = 2;
else CompletionState = 0;
3: CompletionState = 0;
endcase
end
assign KeyReleased = CompletionState == 3 ? 1 : 0;
endmodule
謝謝
#1看起來像一個錯字,只是繼續並將缺少的電線添加到模塊defn。我不明白#2;你是什麼意思「我可以找到別針」,你準確地使用了什麼設置? – Tim
@Tim,我編輯了我的問題。我的意思是:我知道應該分配哪些引腳。 – alicjasalamon
如果這就是你所要求的,那麼你的鍵盤可能實際上並沒有「重置」。如果可用,我只需將它與Altera上的某個按鈕綁定即可。 – Tim