計數器溢出或情況不是肉

Question

我正在CoolRunner 2上運行一個60分鐘計時器的小項目。我想驅動四個7段顯示器來開發VHDL中的新技能，我大多是模擬工程師，所以如果你在VHDL中有任何提示，我會向他們開放。但我的問題是：我有四個計數器一起計數59分59秒，然後重置，但我的第三個計數器不增加（counter3）。當我運行測試臺時，它只能達到59秒，然後重置。

下面我附上了我的櫃檯代碼1,2,3,4。有人能看到任何拼寫錯誤或明顯的錯誤嗎？

--counter1-------------------------------------------------------------  
Process (CLK1Hz,RST,SW1,overflow4) 
begin 
    if (RST = '0') or (overflow4 = '1') then 
     Counter1 <=0; 
    elsif Rising_edge (CLK1Hz)then 
     if (SW1 = '1') then 
      counter1 <= counter1 + 1; 
       if Counter1 = 8 then 
        overflow1 <= '1'; 
       elsif counter1 = 9 then 
        Counter1 <= 0; 
        overflow1 <= '0'; 
       end if; 
     end if; 
end if; 
end process; 

--counter2--------------------------------------------------------------- 
Process (CLK1Hz,RST,SW1,overflow1,overflow4,counter1) 
begin 
    if (RST = '0') or (overflow4 = '1') then 
     Counter2 <=0; 
    elsif Rising_edge (CLK1Hz) then 
     if (SW1 = '1') and (overflow1 = '1') then 
      counter2 <= counter2 + 1; 
       if counter2 = 5 and counter1 = 8 then 
        overflow2 <= '1'; 
       elsif counter2 = 5 and counter1 = 9 then 
        counter2 <= 0; 
        overflow2 <= '0'; 
       end if; 
     end if;  
end if; 
end process; 

--counter3---------------------------------------------------------------- 
Process (CLK1Hz,RST,SW1,overflow2,overflow4,counter1,counter2) 
begin 
    if (RST = '0') or (overflow4 = '1') then 
    Counter3 <=0; 
    elsif Rising_edge (CLK1Hz) then 
     if (SW1 = '1') and (overflow2 = '1') then 
      counter3 <= counter3 + 1; 
       if counter3 = 9 and counter2 = 5 and counter1 = 8 then 
        overflow3 <= '1'; 
       elsif counter3 = 9 and counter2 = 5 and counter1 = 9 then 
        counter3 <= 0; 
        overflow3 <= '0'; 
       end if; 
     end if; 
end if; 
end process;  

--counter4---------------------------------------------------------------- 
Process (CLK1Hz,RST,SW1,overflow3,overflow4,counter1,counter2,counter3) 
begin 
    if (RST = '0') or (overflow4 = '1') then 
     Counter4 <=0; 
    elsif Rising_edge (CLK1Hz) then 
     if(SW1 = '1') and (overflow3 = '1') then 
      counter4 <= counter4 + 1; 
       if counter4 = 6 then 
        counter4 <= 0; 
        overflow4 <= '1'; 
       else overflow4 <= '0'; 
       end if; 
     end if; 
end if; 
end process;  

更新1：這個問題似乎它是整數劑量不接受和功能，所以我嘗試將其轉換爲無符號的，但是這不會女巫出來的問題。

Answer 1

由於overflow2從不設置爲'1'，因此計數器3不遞增。讓我們對過程的時鐘同步部分找counter2：

if (SW1 = '1') and (overflow1 = '1') then 
     counter2 <= counter2 + 1; 
      if counter2 = 5 and counter1 = 8 then 
       overflow2 <= '1'; 
      elsif counter2 = 5 and counter1 = 9 then 
       counter2 <= 0; 
       overflow2 <= '0'; 
      end if; 
    end if;  

寄存器overflow2只能置位，當SW = '1'，overflow1 = '1'，counter2 = 5和counter1 = '8'。但是，overflow1 = '1'和counter1 = 8永遠不會同時發生。當舊值counter1是8時，設置寄存器overflow1，但是然後overflow1將是'1'只有連同counter1 = 9。

您必須在此過程中修復if語句的嵌套，以便只有counter2的增量取決於overflow1。設置overflow2只能取決於計數器狀態（和SW1）。因此，上述已被更改爲：

if (SW1 = '1') then 
    if (overflow1 = '1') then 
     counter2 <= counter2 + 1; 
    end if; 

    if counter2 = 5 and counter1 = 8 then 
     overflow2 <= '1'; 
    elsif counter2 = 5 and counter1 = 9 then 
     counter2 <= 0; 
     overflow2 <= '0'; 
    end if; 
    end if;  

同樣適用於爲counter3和counter4的過程。

在上一個過程中，信號overflow4只能設置，因爲一旦設置，異步復位將永久執行。正如您已經描述的那樣，只需使用counter4的同步重置即可。 overflow4也應該重置其他計數器同步，但我會離開這個練習。

推杆，這一切都在一起，你會得到嵌入到測試平臺與時鐘產生下面的代碼：

library ieee; 
use ieee.std_logic_1164.all; 

entity counter2 is 
end entity counter2; 

architecture counter2 of counter2 is 
    signal counter1, counter2, counter3, counter4 : integer := 0; 
    signal overflow1, overflow2, overflow3, overflow4 : std_logic := '0'; 
    signal RST : std_logic := '1'; 
    signal SW1 : std_logic := '1'; 
    signal CLK1Hz : std_logic := '1'; 

begin -- architecture counter2 

    -- clock generation 
    CLK1Hz <= not CLK1Hz after 500 ms; 

--counter1-------------------------------------------------------------  
    Process (CLK1Hz,RST,SW1,overflow4) 
    begin 
    if (RST = '0') or (overflow4 = '1') then 
     Counter1 <=0; 
    elsif Rising_edge (CLK1Hz)then 
     if (SW1 = '1') then 
     counter1 <= counter1 + 1; 
     if Counter1 = 8 then 
      overflow1 <= '1'; 
     elsif counter1 = 9 then 
      Counter1 <= 0; 
      overflow1 <= '0'; 
     end if; 
     end if; 
    end if; 
    end process; 

--counter2--------------------------------------------------------------- 
    Process (CLK1Hz,RST,SW1,overflow1,overflow4,counter1) 
    begin 
    if (RST = '0') or (overflow4 = '1') then 
     Counter2 <=0; 
    elsif Rising_edge (CLK1Hz) then 
     if (SW1 = '1') then 
     if (overflow1 = '1') then 
      counter2 <= counter2 + 1; 
     end if; 
     if counter2 = 5 and counter1 = 8 then 
      overflow2 <= '1'; 
     elsif counter2 = 5 and counter1 = 9 then 
      counter2 <= 0; 
      overflow2 <= '0'; 
     end if; 
     end if;  
    end if; 
    end process; 

--counter3---------------------------------------------------------------- 
    Process (CLK1Hz,RST,SW1,overflow2,overflow4,counter1,counter2) 
    begin 
    if (RST = '0') or (overflow4 = '1') then 
     Counter3 <=0; 
    elsif Rising_edge (CLK1Hz) then 
     if (SW1 = '1') then 
     if (overflow2 = '1') then 
      counter3 <= counter3 + 1; 
     end if; 

     if counter3 = 9 and counter2 = 5 and counter1 = 8 then 
      overflow3 <= '1'; 
     elsif counter3 = 9 and counter2 = 5 and counter1 = 9 then 
      counter3 <= 0; 
      overflow3 <= '0'; 
     end if; 
     end if; 
    end if; 
    end process;  

--counter4---------------------------------------------------------------- 
    Process (CLK1Hz,RST,SW1,overflow3,overflow4,counter1,counter2,counter3) 
    begin 
    if (RST = '0') then-- or (overflow4 = '1') then 
     Counter4 <=0; 
    elsif Rising_edge (CLK1Hz) then 
     if(SW1 = '1') then 
     if (overflow3 = '1') then 
      counter4 <= counter4 + 1; 
     end if; 

     if counter4 = 6 then 
      counter4 <= 0; 
      overflow4 <= '1'; 
     else overflow4 <= '0'; 
     end if; 
     end if; 
    end if; 
    end process; 

end architecture counter2; 

以下是第100秒模擬截圖：