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任何人都可以幫我弄清楚我的VHDL代碼有什麼問題嗎？下面是代碼：FF /閂鎖和其他警告
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity main is
port(
--50MHz clock
cp : in std_logic;
--reset signal
reset : in std_logic;
--PS/2 data and clock lines
ps2d, ps2c : in std_logic;
--7-segment display segments
segments : out std_logic_vector (7 downto 0);
--anode control
an : out std_logic_vector (3 downto 0);
--data out to LEDs
dout : out std_logic_vector (7 downto 0)
);
end main;
architecture Behavioral of main is
--data from keyboard entity (scancode)
signal data : std_logic_vector (7 downto 0);
--7 segments of display
signal segReg, segNext : std_logic_vector (6 downto 0);
signal tickDone : std_logic;
begin
--just entity that reads PS/2 keyboard data
--rx_done is tick (20 ns)
S1: entity keyboard port map (cp => cp, ps2d => ps2d, ps2c => ps2c,
rx_done => tickDone, dout => data);
dout <= data;
an <= "1110";
segments(6 downto 0) <= segReg;
--turn off dot
segments(7) <= '1';
process (cp, reset)
begin
if reset = '1' then
segReg <= (others => '0');
elsif rising_edge (cp) then
segReg <= segNext;
end if;
end process;
process (tickDone, segReg)
begin
segNext <= segReg;
if tickDone = '1' then
if data = x"16" then
--number 1
segNext <= "1001111";
elsif data = x"1E" then
--number 2
segNext <= "0010010";
elsif data = x"26" then
--number 3
segNext <= "0000110";
elsif data = x"25" then
--number 4
segNext <= "1001100";
else
segNext <= "1111111";
end if;
end if;
end process;
end Behavioral;
當我嘗試合成它/生成編程文件，我得到這些警告：
WARNING:Xst:819 - "C:/VHDL_projekti/PS2K/main.vhd" line 48: The following signals are missing in the process sensitivity list:
WARNING:Xst:2734 - Property "use_dsp48" is not applicable for this technology.
WARNING:Xst:1710 - FF/Latch <segReg_0> (without init value) has a constant value of 0 in block <main>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_1> (without init value) has a constant value of 0 in block <main>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_2> (without init value) has a constant value of 0 in block <main>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_3> (without init value) has a constant value of 0 in block <main>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_4> (without init value) has a constant value of 0 in block <main>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_5> (without init value) has a constant value of 0 in block <main>.
WARNING:Xst:1710 - FF/Latch <segReg_0> (without init value) has a constant value of 0 in block <main>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_1> (without init value) has a constant value of 0 in block <main>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_2> (without init value) has a constant value of 0 in block <main>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_3> (without init value) has a constant value of 0 in block <main>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_4> (without init value) has a constant value of 0 in block <main>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_5> (without init value) has a constant value of 0 in block <main>.
WARNING:Par:288 - The signal reset_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:283 - There are 1 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
WARNING:PhysDesignRules:367 - The signal <reset_IBUF> is incomplete. The signal
有人可以幫助我？我一直在看代碼，我沒有看到任何錯誤，但顯然我做錯了什麼。
1）「以下信號在處理敏感度列表中丟失」這是Xilinx ISE錯誤嗎？我不明白爲什麼我會在第48行的進程靈敏度列表中需要任何其他信號...
2）「由於其他FF/Latch調整，在塊中具有恆定值0」OK，什麼是我做錯了？我不想使用鎖存器......
3）「信號reset_IBUF沒有負載，PAR不會嘗試路由此信號。」這是什麼意思？我的重置信號有什麼問題？爲什麼它不完整？
此代碼是我嘗試在Spartan 3入門板上使用PS/2鍵盤。實體「鍵盤」進行讀取並且它正常工作（當我單獨測試時，我在dout信號上得到正確的掃描碼（我在LED上看到它））。 rx_done是tick（20ns），表示掃描碼已被成功讀取。
所以我只想看看能否以某種方式識別掃描碼（在我的第二個過程中，我正在比較數據信號並將正確的值輸入到segNext信號）並在7段顯示器上顯示某些內容。當我得到這個工作，然後我會實現正確的行爲（檢測所有的掃描代碼，額外的鍵和鍵和關鍵事件）。
我不知道如果我需要別的什麼形容，如果我不請給我留下了評論:)
感謝您的幫助!!!!
編輯：編輯的代碼（添加數據的敏感性列表和別的if語句）：
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity main is
port(
--50MHz clock
cp : in std_logic;
--reset signal
reset : in std_logic;
--PS/2 data and clock lines
ps2d, ps2c : in std_logic;
--7-segment display segments
segments : out std_logic_vector (7 downto 0);
--anode control
an : out std_logic_vector (3 downto 0);
--data out to LEDs
dout : out std_logic_vector (7 downto 0)
);
end main;
architecture Behavioral of main is
--data from keyboard entity (scancode)
signal data : std_logic_vector (7 downto 0);
--7 segments of display
signal segReg, segNext : std_logic_vector (6 downto 0);
signal tickDone : std_logic;
begin
--just entity that reads PS/2 keyboard data
--rx_done is tick (20 ns)
S1: entity keyboard port map (cp => cp, ps2d => ps2d, ps2c => ps2c,
rx_done => tickDone, dout => data);
dout <= data;
an <= "1110";
segments(6 downto 0) <= segReg;
--turn off dot
segments(7) <= '1';
process (cp, reset)
begin
if reset = '1' then
segReg <= (others => '0');
elsif rising_edge (cp) then
segReg <= segNext;
end if;
end process;
process (tickDone, segReg, data)
begin
if tickDone = '1' then
if data = x"16" then
--number 1
segNext <= "1001111";
elsif data = x"1E" then
--number 2
segNext <= "0010010";
elsif data = x"26" then
--number 3
segNext <= "0000110";
elsif data = x"25" then
--number 4
segNext <= "1001100";
else
segNext <= "1111111";
end if;
else
segNext <= segReg;
end if;
end process;
end Behavioral;
不幸的是，這些修改後，我仍然有這樣的警告：
WARNING:Xst:1710 - FF/Latch <segReg_0> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_1> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_2> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_3> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_4> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_5> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_6> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <segReg_0> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_1> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_2> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_3> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_4> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <segReg_5> (without init value) has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Par:288 - The signal reset_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:283 - There are 1 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
謝謝！模擬完成後，我意識到tickDone從未被驅動爲'1'。在檢查鍵盤實體後，我注意到我在我的FSM中犯了錯字（我正在跳過tickDone被驅動爲'1'的最後狀態）...再次感謝:) – xx77aBs 2012-03-15 11:51:24