VHDL：使用輸入端口時創建閂鎖

Question

所以我正在合成一個CPU。

這些都是錯誤的：

WARNING:Xst:1710 - FF/Latch <EXS/mem_address_0> (without init value) has a constant value of 0 in block <Top_level_component>. This FF/Latch will be trimmed during the optimization process. 
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <EXS/mem_address_1> (without init value) has a constant value of 0 in block <Top_level_component>. This FF/Latch will be trimmed during the optimization process. 
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <EXS/mem_address_2> (without init value) has a constant value of 0 in block <Top_level_component>. This FF/Latch will be trimmed during the optimization process. 
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <EXS/mem_address_3> (without init value) has a constant value of 0 in block <Top_level_component>. This FF/Latch will be trimmed during the optimization process. 

然後，它級聯到從這裏一堆其他的東西。

這是給我的錯誤的部分組件：

library ieee; 
use ieee.std_logic_1164.all; 
use ieee.std_logic_arith.all; 
use ieee.std_logic_unsigned.all; 

entity EX_stage is 
    Port( clk : in STD_LOGIC; 
     rst : in STD_LOGIC; 
     mem_opr_in : in STD_LOGIC_VECTOR (1 downto 0); 
     wb_opr_in : in STD_LOGIC; 
     out_opr_in : in STD_LOGIC; 
     alu_mode : in STD_LOGIC_VECTOR (3 downto 0); 
     in1 : in STD_LOGIC_VECTOR (7 downto 0); 
     in2 : in STD_LOGIC_VECTOR (7 downto 0); 
     ra_in : in STD_LOGIC_VECTOR (1 downto 0); 

-- The Ports I'm reading from 
     FW_opcode : in STD_LOGIC_VECTOR (3 downto 0); 
     FW_ra_IN : in STD_LOGIC_VECTOR (1 downto 0); 
     FW_rb_IN : in STD_LOGIC_VECTOR (1 downto 0); 
-- The port I'm writing to 
     mem_address : out STD_LOGIC_VECTOR (7 downto 0); 

     mem_opr_out : out STD_LOGIC_VECTOR (1 downto 0); 
     wb_opr_out : out STD_LOGIC; 
     out_opr_out : out STD_LOGIC; 
     alu_result : out STD_LOGIC_VECTOR (7 downto 0); 
     alu_mode_out : out STD_LOGIC_VECTOR (3 downto 0); 
     ra_out : out STD_LOGIC_VECTOR (1 downto 0); 
     z_flag : out STD_LOGIC; 
     n_flag : out STD_LOGIC); 
end EX_stage; 

architecture Behavioral of EX_stage is 
begin 
    process(clk,rst) 
     variable temp_result: STD_LOGIC_VECTOR (7 downto 0); 
    begin 
    -- Not important... I think 
    end process; 

    process(clk,rst) 
    begin 
     if rst = '1' then 
      mem_address <= (others => '0'); 
     elsif clk = '1' and clk'event then 
      mem_address <= FW_opcode & FW_ra_IN & FW_rb_IN; 
      -- If this is <= x"FF"; then it doesn't give the error 
     end if; 
    end process; 
end Behavioral; 

在頂級部件，我有：

library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 
use IEEE.STD_LOGIC_ARITH.ALL; 
use IEEE.STD_LOGIC_UNSIGNED.ALL; 

entity Top_level_component is 
    Port (portIN : in STD_LOGIC_VECTOR (7 downto 0); 
     portOUT : out STD_LOGIC_VECTOR (7 downto 0); 
     clk :  in STD_LOGIC; 
     rst :  in STD_LOGIC); 
end Top_level_component; 

architecture Behavioral of Top_level_component is 

-- Only the offending components shown 

    component IF_stage 
     port(clk : in STD_LOGIC; 
      rst : in STD_LOGIC; 
      count : in STD_LOGIC_VECTOR (7 downto 0); 
-- All three of these get input to ID_stage AND EX_stage 
      opcode : out STD_LOGIC_VECTOR (3 downto 0); 
      reg_a : out STD_LOGIC_VECTOR (1 downto 0); 
      reg_b : out STD_LOGIC_VECTOR (1 downto 0)); 
    end component; 

    component ID_stage is 
     port(clk : in STD_LOGIC; 
      port_IN : in STD_LOGIC_VECTOR (7 downto 0); 
      opcode : in STD_LOGIC_VECTOR (3 downto 0); 
      ra_IN : in STD_LOGIC_VECTOR (1 downto 0); 
      rb_IN : in STD_LOGIC_VECTOR (1 downto 0); 
      zflag : in STD_LOGIC; 
      nflag : in STD_LOGIC; 
      RD1_IN : in STD_LOGIC_VECTOR (7 downto 0); 
      RD2_IN : in STD_LOGIC_VECTOR (7 downto 0); 
      count : in STD_LOGIC_VECTOR (7 downto 0); 
      previous_opcode : in STD_LOGIC_VECTOR (3 downto 0); 
      MEM_opr : out STD_LOGIC_VECTOR (1 downto 0); 
      WB_opr : out STD_LOGIC; 
      OUT_opr : out STD_LOGIC; 
      ALU_mode : out STD_LOGIC_VECTOR (3 downto 0); 
      RD1_OUT : out STD_LOGIC_VECTOR (7 downto 0); 
      RD2_OUT : out STD_LOGIC_VECTOR (7 downto 0); 
      ra_OUT : out STD_LOGIC_VECTOR (1 downto 0); 
      rb_OUT : out STD_LOGIC_VECTOR (1 downto 0); 
      new_count : out STD_LOGIC_VECTOR (7 downto 0); 
      set_pc : out STD_LOGIC); 
    end component; 

    component EX_stage is 
     port(clk :   in STD_LOGIC; 
      rst :  in STD_LOGIC; 
      mem_opr_in : in STD_LOGIC_VECTOR (1 downto 0); 
      wb_opr_in : in STD_LOGIC; 
      out_opr_in : in STD_LOGIC; 
      alu_mode : in STD_LOGIC_VECTOR (3 downto 0); 
      in1 :  in STD_LOGIC_VECTOR (7 downto 0); 
      in2 :  in STD_LOGIC_VECTOR (7 downto 0); 
      ra_in :   in STD_LOGIC_VECTOR (1 downto 0); 

-- The Offending ports: This is where the signals go in 
      FW_opcode : in STD_LOGIC_VECTOR (3 downto 0); 
      FW_ra_IN : in STD_LOGIC_VECTOR (1 downto 0); 
      FW_rb_IN : in STD_LOGIC_VECTOR (1 downto 0); 
      mem_address : out STD_LOGIC_VECTOR (7 downto 0); 
      mem_opr_out : out STD_LOGIC_VECTOR (1 downto 0); 
      wb_opr_out : out STD_LOGIC; 
      out_opr_out : out STD_LOGIC; 
      alu_result : out STD_LOGIC_VECTOR (7 downto 0); 
      alu_mode_out : out STD_LOGIC_VECTOR (3 downto 0); 
      ra_out : out STD_LOGIC_VECTOR (1 downto 0); 
      z_flag : out STD_LOGIC; 
      n_flag : out STD_LOGIC); 
    end component; 

    -- Signals used 
    signal set_pc : STD_LOGIC := '0'; 
    signal new_count : STD_LOGIC_VECTOR (7 downto 0) := (others => '0'); 
    signal count : STD_LOGIC_VECTOR (7 downto 0) := (others => '0'); 
    signal IF_opcode : STD_LOGIC_VECTOR (3 downto 0) := (others => '0'); 
    signal IF_reg_a : STD_LOGIC_VECTOR (1 downto 0) := (others => '0'); 
    signal IF_reg_b : STD_LOGIC_VECTOR (1 downto 0) := (others => '0'); 
    signal rd_data1 : std_logic_vector(7 downto 0) := (others => '0'); 
    signal rd_data2 : std_logic_vector(7 downto 0) := (others => '0'); 

    signal ID_opcode : STD_LOGIC_VECTOR (3 downto 0) := (others => '0'); 
    signal ID_reg_a : STD_LOGIC_VECTOR (1 downto 0) := (others => '0'); 
    signal ID_reg_b : STD_LOGIC_VECTOR (1 downto 0) := (others => '0'); 
    signal ID_data1 : std_logic_vector(7 downto 0) := (others => '0'); 
    signal ID_data2 : std_logic_vector(7 downto 0) := (others => '0'); 
    signal ID_mem_opr : STD_LOGIC_VECTOR (1 downto 0) := (others => '0'); 
    signal ID_wb_opr : STD_LOGIC := '0'; 
    signal ID_out_opr : STD_LOGIC := '0';   
    signal EX_data1 : std_logic_vector(7 downto 0) := (others => '0'); 
    signal EX_data2 : std_logic_vector(7 downto 0) := (others => '0'); 
    signal EX_reg_a : STD_LOGIC_VECTOR (1 downto 0) := (others => '0'); 
    signal EX_results : STD_LOGIC_VECTOR (7 downto 0) := (others => '0'); 
    signal EX_alu_mode : STD_LOGIC_VECTOR (3 downto 0) := (others => '0'); 
    signal mem_address : STD_LOGIC_VECTOR (7 downto 0) := (others => '0'); 
    signal EX_mem_opr : STD_LOGIC_VECTOR (1 downto 0) := (others => '0'); 
    signal EX_wb_opr : STD_LOGIC := '0'; 
    signal EX_out_opr : STD_LOGIC := '0'; 
    signal z_flag : std_logic := '0'; 
    signal n_flag : std_logic := '0'; 

begin 

    IFS: IF_stage PORT MAP(
     clk => clk, 
     rst => rst, 
     count => count, 
     opcode => IF_opcode, 
     reg_a => IF_reg_a, 
     reg_b => IF_reg_b); 

    IDS: ID_stage port map(
     clk => clk, 
     port_IN => portIN, 
     opcode => IF_opcode, 
     ra_IN => IF_reg_a, 
     rb_IN => IF_reg_b, 
     zflag => z_flag, 
     nflag => n_flag, 
     RD1_IN => rd_data1, 
     RD2_IN => rd_data2, 
     count => count, 
     previous_opcode => EX_alu_mode, 
     MEM_opr => ID_mem_opr, 
     WB_opr => ID_wb_opr, 
     OUT_opr => ID_out_opr, 
     ALU_mode => ID_opcode, 
     RD1_OUT => ID_data1, 
     RD2_OUT => ID_data2, 
     ra_OUT => ID_reg_a, 
     rb_OUT => ID_reg_b, 
     new_count => new_count, 
     set_pc => set_pc); 

    EXS: EX_stage port map( 
     clk => clk, 
     rst => rst, 
     mem_opr_in => ID_mem_opr, 
     wb_opr_in => ID_wb_opr, 
     out_opr_in => ID_out_opr, 
     alu_mode => ID_opcode, 
     in1 => EX_data1, 
     in2 => EX_data2, 
     ra_in => ID_reg_a, 
     FW_opcode => IF_opcode, 
     FW_ra_IN => IF_reg_a, 
     FW_rb_IN => IF_reg_b, 
     mem_address => mem_address, 
     mem_opr_out => EX_mem_opr, 
     wb_opr_out => EX_wb_opr, 
     out_opr_out => EX_out_opr, 
     alu_result => EX_results, 
     alu_mode_out => EX_alu_mode, 
     ra_out => EX_reg_a, 
     z_flag => z_flag, 
     n_flag => n_flag); 

end Behavioral; 

所以在EX_stage，使用時FW_opcode，FW_ra_IN，或FW_rb_IN，我得到錯誤。我不明白。有任何想法嗎？是否我試圖將輸入合併到輸出中？

Answer 1

這不是一個錯誤。這是一個警告，說合成器已經檢測到信號將始終爲0，因此可以將其優化。另外，它和你的標題所表示的閂鎖沒有任何關係（請注意，文字是FF/Latch，它只是表示信號EXS/mem_address_0是觸發器或鎖存器）。

這不一定是壞事，除非你知道他們也應該能夠承擔其他價值。

在這種情況下，我會說你好像FW_ra_IN和FW_rb_IN信號總是0。如果他們應該能夠承擔其他價值，那麼確保他們實際上來自正確的地方。

之所以與x"FF"更換分配的情況下，你沒有得到的警告是，你再有信號時被複位下所有0，和所有1時不是 - 無位的因而不變。

也看看VHDL synthesis warning FF/Latch has a constant value of 0

Answer 2

首先，你貼什麼是警告，而不是錯誤...因此，應阻塞。

但是，警告告訴你，mem_address（3..0）的值始終爲'0'。這意味着，FW_ra_IN和FW_rb_IN總是'0'。這些信號來自您的IF_stage塊（IF_reg_a和IF_reg_b）。檢查是否在IF_stage內更新這些信號。

另一件事是，mem_address不在top_level塊內使用。因此可能會在優化期間被合成器刪除。