如何使用16位LFSR創建僞隨機序列

Question

我試圖生成16位隨機序列。 問題是輸出處於未定義狀態。我覺得這是由於這些異或聲明中的並行處理。所以我拖延了，但它仍然不起作用。

library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 
use IEEE.STD_LOGIC_ARITH.ALL; 
use IEEE.STD_LOGIC_UNSIGNED.ALL; 

entity random_data_generator is 
    port (
    por    : in STD_LOGIC; 
    sys_clk   : in STD_LOGIC; 
    random_flag  : in STD_LOGIC; 
    random_data  : out STD_LOGIC_vector (15 downto 0) 
); 
end random_data_generator; 

architecture Behavioral of random_data_generator is 
    signal q   : std_logic_vector(15 downto 0); 
    signal n1,n2,n3 : std_logic; 


begin 
    process(sys_clk) 
    begin 
    if(por='0') then 
    q<= "1001101001101010"; 
    elsif(falling_edge(sys_clk)) then 
     if(random_flag='1') then 
     n1<= q(15) xor q(13); 
     n2<= n1 xor q(11) after 10 ns; 
     n3<= n2 xor q(10) after 10 ns; 
     q<= q(14 downto 0) & n3 after 10 ns; 
    end if; 
    end if; 
    end process; 
    random_data <= q; 
end Behavioral; 

Answer 1

使您LFSR一些小的結構性變化：

library ieee; 
use ieee.std_logic_1164.all; 

entity random_data_generator is 
    port (
     por:    in std_logic; 
     sys_clk:   in std_logic; 
     random_flag:  in std_logic; 
     random_data:  out std_logic_vector (15 downto 0) 
    ); 
end entity random_data_generator; 

architecture behavioral of random_data_generator is 
    signal q:    std_logic_vector(15 downto 0); 
    signal n1, n2, n3: std_logic; 
begin 
    process (por, sys_clk) -- ADDED por to sensitivity list 
    begin 
     if por = '0' then 
      q <= "1001101001101010"; 
     elsif falling_edge(sys_clk) then 
      if random_flag = '1' then 
       -- REMOVED intermediary products as flip flops 
       q <= q(14 downto 0) & n3; -- REMOVED after 10 ns; 
      end if; 
     end if; 
    end process; 
    -- MOVED intermediary products to concurrent signal assignments: 
    n1 <= q(15) xor q(13); 
    n2 <= n1 xor q(11); -- REMOVED after 10 ns; 
    n3 <= n2 xor q(10); -- REMOVED after 10 ns; 

    random_data <= q; 
end architecture behavioral; 

這些變化刪除N1，N2和N3翻轉通過促進這些任務併發信號賦值語句無人問津。產生'U'的根本問題是這些觸發器沒有初始化。它們是觸發器，因爲它們的分配在sys_clk下降沿處具有elsif條件的if語句內。

添加測試平臺：

library ieee; 
use ieee.std_logic_1164.all; 

entity rng_tb is 
end entity; 

architecture foo of rng_tb is 
    signal por:   std_logic; 
    signal sys_clk:  std_logic := '0'; 
    signal random_flag: std_logic; 
    signal random_data: std_logic_vector (15 downto 0); 
begin 
DUT: 
    entity work.random_data_generator 
     port map (
      por => por, 
      sys_clk => sys_clk, 
      random_flag => random_flag, 
      random_data => random_data 
     ); 
CLOCK: 
    process 
    begin 
     wait for 5 ns; 
     sys_clk <= not sys_clk; 
     if now > 2800 ns then 
      wait; 
     end if; 
    end process; 
STIMULI: 
    process 
    begin 
     por <= '1'; 
     random_flag <= '0'; 
     wait until falling_edge(sys_clk); 
     por <= '0'; 
     wait until falling_edge(sys_clk); 
     wait for 1 ns; 
     por <= '1'; 
     wait until falling_edge(sys_clk); 
     random_flag <= '1'; 
     wait; 
    end process; 
end architecture; 

判斷兩者，闡述和模擬的測試平臺，給出：

使用一個16位的顯示用的長度的僞隨機序列長於16線性反饋移位寄存器（LFSR）。