沒有可行的中綴運算符條目「=」[VHDL]

Question

我一直在寫一個交通燈控制器的狀態機。

-- Ampelsteuerung mit Zähler und FSM Componente 

library ieee; 
use ieee.std_logic_1164.all; 
use ieee.std_logic_unsigned.all; 
use ieee.numeric_std.all; 

entity AMPLSTRG is 
    port ( CLK, B1, RES : in bit; 
      MAINRE, MAINYE, MAINGR : out bit; 
      FARMRE, FARMYE, FARMGR : out bit); 
end AMPLSTRG; 

architecture FUNKTION of AMPLSTRG is 
type AMP_STATE is (S0, S1, S2, S3, S4, S5, S6, S7, S8); -- Typendefinition 
signal SCLR : bit; 
signal CYCLES : unsigned (4 downto 0); 
signal STATE, NEXT_STATE : AMP_STATE;     -- STATE = aktueller Status, NEXT_STATE nächster Status (Typenzuweisung) 
begin 
-- COUNTER Prozess 
CO: process (CLK) 
begin 
    if CLK = '1' and CLK'event then 
     if SCLR = '1' then 
      CYCLES <= (others => '0');     -- 'others' = gesamten Vektor auf '0' setzten 
     else 
      CYCLES <= CYCLES + 1; 
     end if; 
    end if; 
end process CO; 

AMP_SYNC: process (CLK, RES) 
begin 
    if RES = '1' then 
     STATE <= S0 after 5 ns; 
     SCLR <= '1' after 5 ns; 
    elsif CLK = '1' and CLK'event then 
     STATE <= NEXT_STATE after 5 ns;     -- Zustandszuweisung 
    end if; 
end process AMP_SYNC; 

AMP_KOMB: process (STATE, B1, CYCLES) 
begin 
    -- default Werte Setzen 
    MAINRE <= '0' after 5 ns; 
    MAINYE <= '0' after 5 ns; 
    MAINGR <= '0' after 5 ns; 

    FARMRE <= '0' after 5 ns; 
    FARMYE <= '0' after 5 ns; 
    FARMGR <= '0' after 5 ns; 

    NEXT_STATE <= STATE; 
    SCLR <= '0'; 

    case STATE is 
     when S0 => if B1 = '1' then 
         MAINGR <= '1' after 5 ns; 
         FARMRE <= '1' after 5 ns; 
         NEXT_STATE <= S1 after 5 ns; 
         SCLR <= '1' after 5 ns; 
        else        -- MAINGR | FARMRE until B1 pressed 
         MAINGR <= '1' after 5 ns; 
         FARMRE <= '1' after 5 ns; 
         SCLR <= '1' after 5 ns; 
        end if; 

     when S1 => if CYCLES = '5' then 
         MAINGR <= '0' after 5 ns; 
         MAINYE <= '1' after 5 ns;    
         NEXT_STATE <= S2 after 5 ns; 
         SCLR <= '1'; 
        else        -- MAINGR | FARMRE for 5 sec 
         MAINGR <= '1' after 5 ns; 
         FARMRE <= '1' after 5 ns; 
        end if; 

     when S2 => if CYCLES = '5' then       MAINRE <= '1' after 5 ns; 
         FARMRE <= '1' after 5 ns;    
         NEXT_STATE <= S3 after 5 ns; 
         SCLR <= '1'; 
        else        -- MAINYE | FARMRE for 5 sec 
         MAINYE <= '1' after 5 ns; 
         FARMRE <= '1' after 5 ns; 
        end if; 

     when S3 => if CYCLES = '2' then 
         MAINRE <= '1' after 5 ns; 
         FARMRE <= '1' after 5 ns; 
         FARMYE <= '1' after 5 ns;    
         NEXT_STATE <= S4 after 5 ns; 
         SCLR <= '1'; 
        else        -- MAINRE | FARMRE for 2 sec 
         MAINRE <= '1' after 5 ns; 
         FARMRE <= '1' after 5 ns; 
        end if; 

     when S4 => if CYCLES = '2' then 
         MAINRE <= '1' after 5 ns; 
         FARMGR <= '1' after 5 ns;   
         NEXT_STATE <= S5 after 5 ns; 
         SCLR <= '1'; 
        else        -- MAINRE | FARMRE | FARMYE for 2 sec 
         MAINRE <= '1' after 5 ns; 
         FARMRE <= '1' after 5 ns; 
         FARMYE <= '1' after 5 ns; 
        end if; 

     when S5 => if CYCLES = '30' then 
         MAINRE <= '1' after 5 ns; 
         FARMYE <= '1' after 5 ns;   
         NEXT_STATE <= S6 after 5 ns; 
         SCLR <= '1'; 
        else        -- MAINRE | FARMGR for 30 sec 
         MAINRE <= '1' after 5 ns; 
         FARMGR <= '1' after 5 ns; 
        end if; 

     when S6 => if CYCLES = '5' then 
         MAINRE <= '1' after 5 ns; 
         FARMRE <= '1' after 5 ns;   
         NEXT_STATE <= S7 after 5 ns; 
         SCLR <= '1'; 
        else        -- MAINRE | FARMYE for 5 sec 
         MAINRE <= '1' after 5 ns; 
         FARMYE <= '1' after 5 ns; 
        end if; 

     when S7 => if CYCLES = '2' then 
         MAINRE <= '1' after 5 ns; 
         MAINYE <= '1' after 5 ns; 
         FARMRE <= '1' after 5 ns;  
         NEXT_STATE <= S8 after 5 ns; 
         SCLR <= '1'; 
        else        -- MAINRE | FARMRE for 2 sec 
         MAINRE <= '1' after 5 ns; 
         FARMRE <= '1' after 5 ns;  
        end if; 

     when S8 => if CYCLES = '2' then 
         MAINGR <= '1' after 5 ns; 
         FARMRE <= '1' after 5 ns;   
         NEXT_STATE <= S0 after 5 ns; 
         SCLR <= '1'; 
        else        -- MAINRE | MAINYE | FARMRE for 2 sec 
         MAINRE <= '1' after 5 ns; 
         MAINYE <= '1' after 5 ns; 
         FARMRE <= '1' after 5 ns;  
        end if; 

end process AMP_KOMB; 
end FUNKTION; 

在編譯時在的ModelSim PE學生我收到以下錯誤代碼：

No feasible entries for infix operator "=" 

嘗試許多不同的圖書館我無法找到任何解決方案來解決這個錯誤後。我想這是一個錯誤的庫或錯誤的使用「=」運算符的問題。

下面是從Modelsim的完整的錯誤報告：

** Error: [...]/AMPSTR.vhdl(68): No feasible entries for infix operator "=". 
** Error: [...]/AMPSTR.vhdl(68): Type error resolving infix expression "=" as type std.STANDARD.BOOLEAN. 
** Error: [...]/AMPSTR.vhdl(78): No feasible entries for infix operator "=". 
** Error: [...]/AMPSTR.vhdl(78): Type error resolving infix expression "=" as type std.STANDARD.BOOLEAN. 
** Error: [...]/AMPSTR.vhdl(87): No feasible entries for infix operator "=". 
** Error: [...]/AMPSTR.vhdl(87): Type error resolving infix expression "=" as type std.STANDARD.BOOLEAN. 
** Error: [...]/AMPSTR.vhdl(98): No feasible entries for infix operator "=". 
** Error: [...]/AMPSTR.vhdl(98): Type error resolving infix expression "=" as type std.STANDARD.BOOLEAN. 
** Error: [...]/AMPSTR.vhdl(109): near "'": syntax error 
** Error: [...]/AMPSTR.vhdl(114): near "else": expecting END or WHEN 
** Error: [...]/AMPSTR.vhdl(117): near "if": expecting PROCESS 

Answer 1

你錯過了一個

end case; 

前右

end process AMP_KOMB; 

您使用了錯誤的數字包，因爲你使用你應該用numeric_bit位類型。你不應該混合std_logic_unsigned和numeric_xxx：

library ieee; 
-- use ieee.std_logic_1164.all; 
-- use ieee.std_logic_unsigned.all; 
-- use ieee.numeric_std.all; 
use ieee.numeric_bit.all; 

CYCLES的陣列長度爲5，索引範圍(4 downto 0)。用於與它使用上可接受的文字應的位串：

when S1 => if CYCLES = '5' then 

應該是：

when S1 => if CYCLES = "00101" then 

等（每一個地方CYCLES被評估）。請注意，'30'不是一個字符字面量，在位字符串中有三十個字符是"11110"。

修復所有這些和你的VHDL設計規範分析和闡述。沒有寫測試臺，我沒有模擬它。

在看到Brian的回答後，值得指出的是numeric_bit還有一個unsigned的類型聲明以及關聯的運算符。

Answer 2

在if CYCLES = '5' then你能指望什麼發生？

CYCLES是UNSIGNED。無論是numeric_std.unsigned還是來自其他非標準庫的某種其他類型的UNSIGNED，我都看不出來，但我建議只使用numeric_std庫。

'5'在這種情況下是字符文字，不像5這是一個整數文字。根據錯誤信息，編譯器顯然找不到UNSIGNED和字符之間的相等運算符。

在if B1 = '1' then,'1'可以是字符文字或位文字;兩者都是可見的，但只有一個是有意義的（爲其定義了一個相等運算符），所以編譯器對此表達式沒有任何問題。

Answer 3

有其不被大衛和Brian之前解決了一些問題，除了：

• 您當前的狀態信號應該有一個默認的分配，因爲它映射到一個寄存器。
• 您的信號SCLR有多個驅動程序。只有一個進程應該爲信號賦值。如果需要的話，在這兩個進程之間實現一個「通信協議」。
• 您使用的是枚舉類型的國家名稱，而不是一個整數（這是很好的），所以請選擇正確的枚舉成員的名字，以提高你的代碼:)