移植寄存器爲std_logic_vector在VHDL

Question

有人可以告訴我，如何使移位寄存器的12位std_logic_vector項目？

Answer 1

看看下面的例子。 VECTOR_WIDTH是每個std_logic_vector（12，在你的情況）中的位數。 FIFO_DEPTH是您在移位寄存器中需要的向量數。

library ieee; 
use ieee.std_logic_1164.all; 

entity vectors_fifo is 
    generic (
     VECTOR_WIDTH: natural := 12; 
     FIFO_DEPTH: natural := 100 
    ); 
    port (
     clock: in std_logic; 
     reset: in std_logic; 
     input_vector: in std_logic_vector(VECTOR_WIDTH-1 downto 0); 
     output_vector: out std_logic_vector(VECTOR_WIDTH-1 downto 0) 
    ); 
end; 

architecture rtl of vectors_fifo is 
    type fifo_memory_type is array (natural range <>) of std_logic_vector; 
    signal fifo_memory: fifo_memory_type(0 to FIFO_DEPTH-1)(VECTOR_WIDTH-1 downto 0); 
begin 
    process (clock, reset) begin 
     if reset then 
      fifo_memory <= (others => (others => '0')); 
     elsif rising_edge(clock) then 
      fifo_memory <= input_vector & fifo_memory(0 to FIFO_DEPTH-2); 
     end if; 
    end process; 

    output_vector <= fifo_memory(FIFO_DEPTH-1); 
end;