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我已經用VHDL編寫了一個簡單的實體來閃爍LED,並試圖在ModelSim中模擬它,但是在輸出上沒有轉換。ModelSim Simulator中沒有實體輸出 - VHDL
下面是LED_Blink
實體我的HDL文件:
Library IEEE;
use IEEE.Std_logic_1164.all;
entity LED_Blink is
generic (
g_SYSTEM_CLOCK_PERIOD : in time := 10 ns; -- 100 MHz clock period
g_LED_ON_TIME : in time := 1 sec
);
port(
system_clock : in Std_logic;
reset_fpga_L : in Std_logic;
led_out : out Std_logic
);
end entity LED_Blink;
architecture RTL of LED_Blink is
signal led_state : Std_logic;
constant COUNTER_RELOAD_VAL : natural := g_LED_ON_TIME/g_SYSTEM_CLOCK_PERIOD;
begin
process(reset_fpga_L, system_clock)
variable counter : natural range 0 to COUNTER_RELOAD_VAL := COUNTER_RELOAD_VAL;
begin
if reset_fpga_L = '0' then
counter := COUNTER_RELOAD_VAL;
led_state <= '0';
elsif rising_edge(system_clock) then
if counter = 0 then
led_state <= not led_state;
counter := COUNTER_RELOAD_VAL;
else
counter := counter - 1;
end if;
end if;
led_out <= led_state;
end process;
end architecture RTL;
這裏是我的測試臺:
Library IEEE;
use IEEE.Std_logic_1164.all;
entity LED_Blink_TB is
end entity LED_Blink_TB;
architecture RTL of LED_Blink_TB is
signal reset_fpga_L : Std_logic := '0';
signal system_clock : Std_logic := '0';
signal led_out : Std_logic := '0';
begin
G1: entity work.LED_Blink(RTL) port map(reset_fpga_L, system_clock, led_out);
CLK: process
begin
while now <= 5 sec loop
system_clock <= not system_clock;
wait for 5 ns;
end loop;
wait;
end process CLK;
STIM: process
begin
reset_fpga_L <= '0';
wait for 100 ns;
reset_fpga_L <= '1';
wait for 4 sec;
reset_fpga_L <= '0';
wait for 50 ns;
reset_fpga_L <= '1';
wait;
end process STIM;
end architecture RTL;
我想不通,爲什麼我沒有看到任何轉換在led_out
上,當我在模擬器中運行我的測試臺時。我已經注意將system_clock
,reset_fpga_L
和led_out
的波添加到跟蹤視圖。你看到我的代碼中有什麼可能是個問題嗎?謝謝你的幫助。
我可以看到的唯一問題是1秒鐘是很多仿真時間......我將LED_ON_TIME設置爲1 ms甚至10 us,位於測試臺實體化實體中的通用映射中。 –
只給了一個嘗試,結果相同 – Kashif
稍微不同的[testbench](https://i.stack.imgur.com/R7GHF.jpg)將泛型設置爲100 ms時鐘週期和500 ms led_on這[波形](https://i.stack.imgur.com/piVbt.png)。模擬多少努力取決於多少次轉換。 – user1155120