-2
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity TopLevel is
Port (reset : in std_logic;
clock : in std_logic;
coin : in std_logic;
push : in std_logic;
count1 : out std_logic_vector(15 downto 0)
);
end TopLevel;
architecture Modular of TurnstileDetector is
signal unlock : std_logic;
begin
controller: entity TurnstileDetectorController
Port map (reset => reset,
clock => clock,
coin => coin,
push => push,
unlock => unlock
);
counter: entity work.counter
Port map (reset => reset,
clock => clock,
cen => unlock,
q => count1
);
end architecture Modular;
錯誤頂層VHDL： **錯誤：（VCOM-11）找不到work.turnstiledetector。錯誤：上的ModelSim
**錯誤：C：/Modeltech_pe_edu_10.4a/examples/TopLevel.vhd（14）：VHDL編譯器退出
錯誤如何能夠解決？ – Bekbol
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