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我嘗試實現具有異步預設和清除功能的JK觸發器,並在時鐘上具有正邊沿邏輯。VHDL錯誤錯誤(10822):無法實現賦值寄存器
我收到以下錯誤Altera提供的Quartus II:
Error (10822): HDL error at JK_FF_PE_D1.vhd(52): couldn't implement registers for assignments on this clock edge
Error: Can't elaborate top-level user hierarchy
我沒有看到錯誤......我將成爲一個尖頭或忠告,真的很感謝。
預先感謝您!
library ieee;
use ieee.std_logic_1164.all;
entity JK_FF_PE_D1 is
port(
J, K : in std_logic; -- J, K inputs of flip flop
PS : in std_logic; -- Preset of flip flop
CLR : in std_logic; -- CLR of flip flop
CLK : in std_logic; -- Clock
Q, Qcompl : out std_logic -- Q and its complementary output
);
end entity JK_FF_PE_D1;
architecture simple of JK_FF_PE_D1 is
signal temp_Q, temp_Qcompl : std_logic;
begin
p0:process(PS, CLR, CLK) is
begin
case std_logic_vector'(PS, CLR) is
when "00" =>
temp_Q <= '1';
temp_Qcompl <= '1';
when "01" =>
temp_Q <= '1';
temp_Qcompl <= '0';
when "10" =>
temp_Q <= '0';
temp_Qcompl <= '1';
when others => -- Preset = 1 , Clear = 1
if rising_edge (CLK) then -- Clock turns from 0 -> 1
case std_logic_vector'(J, K) is
when "11" =>
temp_Q <= not temp_Q;
temp_Qcompl <= not temp_Qcompl;
when "10" =>
temp_Q <= '1';
temp_Qcompl <= '0';
when "01" =>
temp_Q <= '0';
temp_Qcompl <= '1';
when others =>
null;
end case;
end if;
end case;
end process p0;
Q <= temp_Q;
Qcompl <= not temp_Qcompl;
end architecture simple;
非常感謝您的幫助......我想改變這種情況,但是我承認它會是一個非常愚蠢的編譯器限制......謝謝 –
模板匹配 - 編譯器看到if ..elsif鏈作爲一組異步預置/清零指令後跟一個時鐘控制的一部分。這與其觸發器的模板相匹配。案例陳述雖然描述相同的行爲,但並未被認可。看看XST和Synplify是否可以管理它會很有趣......(預測:XST不能,Synplify可以) –