vhdl代碼錯誤

我是vhdl的新手。我有我的代碼如下（子編編譯非常好）。我無法修復以下錯誤vhdl代碼錯誤

**錯誤：C：/ Users/acer/Desktop/alu new/ALU_VHDL.vhd（110）：非法的順序語句。 **錯誤：C：/ Users/acer/Desktop/alu new/ALU_VHDL.vhd（115）：非法順序語句。 **錯誤：C：/ Users/acer/Desktop/alu new/ALU_VHDL.vhd（120）：非法的順序語句。 **錯誤：C：/ Users/acer/Desktop/alu new/ALU_VHDL.vhd（128）：非法順序語句。 **警告：[14] C：/ Users/acer/Desktop/alu new/ALU_VHDL.vhd（128）：（vcom-1272）正式的「剩餘」長度爲4;的實際長度爲8

**錯誤：C：/用戶/宏基/桌面/ ALU新/ ALU_VHDL.vhd（138）：VHDL編譯器退出

行號是在這裏的代碼粗體那些。他們是portmap ones 任何人都可以請幫助我與此。這將是非常友善的你。

library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 
use IEEE.NUMERIC_STD.ALL; 

entity ALU_VHDL is 
    port 
    (
     OperandA : in std_logic_vector(3 downto 0); 
     OperandB : in std_logic_vector(3 downto 0); 
     Operation: in std_logic_vector(2 downto 0); 
     Startt : in std_logic; 
     Ready : out std_logic; 
     Result_High : out std_logic_vector(3 downto 0); 
     Result_Low : out std_logic_vector(7 downto 0); 
     Errorsig : out std_logic; 
     Reset_n : in std_logic; 
     Clkk : in std_logic); 
end entity ALU_VHDL; 

architecture Behavioral of ALU_VHDL is 
-- And gate 
component AND_gate 
    port( 
    x,y : IN std_logic_vector(3 downto 0); 
    z : OUT std_logic_vector(3 downto 0)); 
end component; 

-- OR Gate 
component OR_gate 
    port( 
    x,y : IN std_logic_vector(3 downto 0); 
    z : OUT std_logic_vector(3 downto 0)); 
end component; 
-- XOR gate 

component XOR_gate 
    port( 
    x,y : IN std_logic_vector(3 downto 0); 
    z : OUT std_logic_vector(3 downto 0)); 
end component; 
-- Adder 

COMPONENT adder4 
PORT 
    (
    C : IN std_logic; 
    x,y : IN std_logic_vector(3 DOWNTO 0); 
    R : OUT std_logic_vector(3 DOWNTO 0); 
    C_out : OUT std_logic); 
END COMPONENT; 

-- Subtractor 
COMPONENT Substractor4 
PORT 
     (
     br_in : IN std_logic; 
     x,y : IN std_logic_vector(3 DOWNTO 0); 

     R : OUT std_logic_vector(3 DOWNTO 0); 
     E : out std_logic); 
END COMPONENT; 

-- Multiplier 
COMPONENT mult4by4 
    port(operA, operB: in std_logic_vector(3 downto 0); 
    sumOut: out std_logic_vector(7 downto 0)); 
END COMPONENT; 

-- Division 
COMPONENT Division 
Port (Dividend : in std_logic_vector(3 downto 0); 
      Divisor : in std_logic_vector(3 downto 0); 
      Start : in std_logic; 
      Clk :  in std_logic; 
      Quotient : out std_logic_vector(3 downto 0); 
      Remainder : out std_logic_vector(3 downto 0); 
      Finish : out std_logic); 
END COMPONENT; 

begin 

    process(OperandA, OperandB, Startt, Operation) is 
    begin 


     case Operation is 

      when "000" => 
       Result_High <= "XXXX"; 


      when "001" => 
       Result_High <= OperandA and OperandB; 


       when "010" => 
      Result_High <= OperandA or OperandB; 


      when "011" => 
      Result_High <= OperandA xor OperandB; 



      when "100" => 
      -- Adder 
       **U05 : adder4 PORT MAP (C=>Startt,x=>OperandA,y=>OperandB,R=>Result_High,C_out=>Ready);** 


      when "101" => 
      -- Substractor & Error signal 
       **U06 : Substractor4 PORT MAP (br_in=>Startt,x=>OperandA,y=>OperandB,R=>Result_High,E=>Errorsig);** 


      when "110" => 
       -- multiplication 
      **U07 : mult4by4 PORT MAP (operA=>OperandA,operB=>OperandB,sumOut=>Result_Low);** 


      when "111" => 
       -- Division 
       if (OperandB ="0000") then 
        Errorsig <= '1'; 
       else 
      **U08 : Division PORT MAP (Dividend=>OperandA,Divisor=>OperandB,Start=>Startt,Clk=>Clkk,Quotient=>Result_High,Remainder=>Result_Low,Finish=>Ready);** 
       end if; 

       when others => 
       Errorsig <= '1'; 

     end case; 

    end process; 

end architecture Behavioral;

來源

2013-12-17 user3113283

'portmap'的用途是什麼？ – shrm