我在使用這段代碼時遇到了一些麻煩。看起來狀態S0總是有效的,即使它不應該是。看起來這個狀態的輸出是反轉的(當它被禁止時是有效的)。有任何想法嗎?底部的模擬打印。由於VHDL爲什麼當狀態S0不應該是活動狀態?
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity ControlUnit is
port(clk : in std_logic;
reset : in std_logic;
validTime : in std_logic;
timeData : in std_logic_vector(3 downto 0);
writeEnable : out std_logic;
writeAddress : out std_logic_vector(3 downto 0);
averageReady : out std_logic);
end ControlUnit;
architecture Behavioral of ControlUnit is
type TState is (S0, S1, S2, S3, S4, S5);
signal PState, NState: TState;
begin
sync_proc: process(clk, reset)
begin
if(reset = '1') then
PState <= S0;
elsif(rising_edge(clk)) then
PState <= NState;
end if;
end process;
comb_proc: process(PState, validTime, timeData)
begin
averageReady <= '0';
writeEnable <= '0';
case PState is
when S0 =>
if(validTime = '1') then
writeEnable <= '1';
NState <= S1;
else
NState <= S0;
end if;
when S1 =>
if(validTime = '1') then
writeEnable <= '1';
NState <= S2;
else
NState <= S1;
end if;
when S2 =>
if(validTime = '1') then
writeEnable <= '1';
NState <= S3;
else
NState <= S2;
end if;
when S3 =>
if(validTime = '1') then
writeEnable <= '1';
NState <= S4;
else
NState <= S3;
end if;
when S4 =>
if(validTime = '1') then
writeEnable <= '1';
NState <= S5;
else
NState <= S4;
end if;
when S5 =>
averageReady <= '1';
NState <= S0;
when others =>
NState <= S0;
end case;
end process;
with PState select
writeAddress <= "0000" when S0,
"0001" When S1,
"0010" when S2,
"0011" when S3,
"0100" when S4,
"XXXX" when others;
end Behavioral;
這裏是模擬的打印:
這似乎是一個熱門編碼(暗示這是後合成模擬)。 PState.S0的極性看起來是倒置的,而其餘的看起來是正確的。合成的硬件需要保持極性直線,但PState不是輸出,它是否正確模擬?您尚未提供允許預綜合模擬的[最小,完整和可驗證示例](http://stackoverflow.com/help/mcve)。 *任何想法?*對於一個問題有點寬泛。如果你想要在內部進行同步,也許你可以以不同的方式限制合成。 – user1155120