Yosys優化走環形振盪器上ice40 FPGA

Question

我試着去實現一個簡單的環形振盪器的使用ice40 FPGA yosys（0.7）如下：

module ringosc(input clkin, 
       output out); 

    (* keep="true" *) 
    wire [100:0]    ring; 

    assign ring[100:1] = ~ring[99:0]; 
    assign ring[0]  = ~ring[100]; 

    assign out = ring[0]; 

endmodule 

但是，它似乎得到優化，即使我使用keep屬性。我可以在yosys日誌輸出中看到這一點：

7.14.2. Executing OPT_EXPR pass (perform const folding). 
Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$292' (double_invert) in module `\lfsr' with constant driver `\trng.ring [62] = \trng.ring [60]'. 
Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$293' (double_invert) in module `\lfsr' with constant driver `\trng.ring [63] = \trng.ring [59]'. 
Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$294' (double_invert) in module `\lfsr' with constant driver `\trng.ring [64] = \trng.ring [58]'. 
Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$295' (double_invert) in module `\lfsr' with constant driver `\trng.ring [65] = \trng.ring [57]'. 
Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$296' (double_invert) in module `\lfsr' with constant driver `\trng.ring [66] = \trng.ring [56]'. 
Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$297' (double_invert) in module `\lfsr' with constant driver `\trng.ring [67] = \trng.ring [55]'. 
Replacing $_NOT_ cell `$auto$simplemap.cc:37:simplemap_not$298' (double_invert) in module `\lfsr' with constant driver `\trng.ring [68] = \trng.ring [54]'. 
... 

如何防止yosys這樣做？

Answer 1

實例化邏輯單元手動地，就像是在此實例中的項目來完成： http://svn.clifford.at/handicraft/2015/ringosc/

（該項目是從該視頻I在2015年提出：
https://www.youtube.com/watch?v=UFqWjZudOho）