比較器的Verilog測試平臺錯誤

我是Verilog的新手，當a等於，小於，大於b時，我需要製作一個8位比較器。下面是我的代碼（這使我沒有任何錯誤）：比較器的Verilog測試平臺錯誤

module MagnitudeComparator8bit (input signed [7:0]a, 
           input signed [7:0]b, 
           output eq, 
           output lt, 
           output gt); 
    assign eq = a == b; 
    assign lt = a < b; 
    assign gt = a > b; 
endmodule

這裏就是我的測試平臺，但是當我運行模擬，我碰上了多個錯誤，但我不知道我錯了。任何幫助？

module MagnitudeComparatorTestbench; 
    reg [7:0] a, b; 
    wire eq, lt, gt; 

    MagnitudeComparator8bit uut(
     .a(a), 
     .b(b), 
     .eq(eq), 
     .lt(lt), 
     .gt(gt) 
    ); 

    initial begin 
      $monitor (「%d %b %b %d %d %d」, $time, a, b, eq, lt, gt); 
      a=8’b11110000; 
      b=8’b11110000; 
     #10 a=8’b1001001; 
      b=8’b10101010; 
     #10 a=8’b11001100; 
      b=8’b10101000; 
     #10 $finish 
    end 
endmodule

錯誤：

testbench.sv:14: error: unmatched character (hex ?) 
testbench.sv:e: error: unmatched character (hex ?) 
testbench.sv:e: error: unmatched character (hex ?) 
testbench.sv:e: syntax error 
testbench.sv:e: error: unmatched character (hex ?) 
testbench.sv:e: error: unmatched character (hex ?) 
testbench.sv:e: error: unmatched character (hex ?) 
testbench.sv:e: error: malformed statement 
testbench.sv:f: error: unmatched character (hex ?) 
testbench.sv:f: error: unmatched character (hex ?) 
testbench.sv:f: error: unmatched character (hex ?) 
testbench.sv:f: syntax error 
testbench.sv:f: error: malformed statement 
testbench.sv:10: error: unmatched character (hex ?) 
testbench.sv:10: error: unmatched character (hex ?) 
testbench.sv:10: error: unmatched character (hex ?) 
testbench.sv:10: syntax error 
testbench.sv:10: error: malformed statement 
testbench.sv:11: error: unmatched character (hex ?) 
testbench.sv:11: error: unmatched character (hex ?) 
testbench.sv:11: error: unmatched character (hex ?) 
testbench.sv:11: syntax error 
testbench.sv:11: error: malformed statement 
testbench.sv:12: error: unmatched character (hex ?) 
testbench.sv:12: error: unmatched character (hex ?) 
testbench.sv:12: error: unmatched character (hex ?) 
testbench.sv:12: syntax error 
testbench.sv:12: error: malformed statement 
testbench.sv:13: error: unmatched character (hex ?) 
testbench.sv:13: error: unmatched character (hex ?) 
testbench.sv:13: error: unmatched character (hex ?) 
testbench.sv:13: syntax error 
testbench.sv:13: error: malformed statement 
testbench.sv:14: error: unmatched character (hex ?) 
testbench.sv:14: error: unmatched character (hex ?) 
testbench.sv:14: error: unmatched character (hex ?) 
testbench.sv:14: syntax error 
testbench.sv:14: error: malformed statement 
testbench.sv:16: syntax error 
Exit code expected: 0, received: 40

來源

2016-01-28 smd

您的帖子奇怪引號字符。在我複製和粘貼你的代碼後，這些給了我錯誤。我修正了報價。複製此代碼：

module MagnitudeComparatorTestbench; 
    reg [7:0] a, b; 
    wire eq, lt, gt; 

    MagnitudeComparator8bit uut(
     .a(a), 
     .b(b), 
     .eq(eq), 
     .lt(lt), 
     .gt(gt) 
    ); 

    initial begin 
      $monitor ("%d %b %b %d %d %d", $time, a, b, eq, lt, gt); 
      a=8'b11110000; 
      b=8'b11110000; 
     #10 a=8'b1001001; 
      b=8'b10101010; 
     #10 a=8'b11001100; 
      b=8'b10101000; 
     #10 $finish; 
    end 
endmodule

我也在$完成後添加了一個半。

來源

2016-01-29 00:32:10 toolic

我試過你的代碼，唯一的問題是$完成後缺少分號。所以＃10 $完成;

來源

2016-01-29 00:35:25 DBB

比較器的Verilog測試平臺錯誤

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