使用計數器

Question

我試圖運行我利用我的櫃檯來輸入3-7譯碼器，所有的個體代碼運行良好，但結構性的代碼是給了一些錯誤運行3至7解碼器

這是我的櫃檯節目

library IEEE; 

use IEEE.std_logic_1164.all; 

use IEEE.std_logic_unsigned.all; 

entity counter is 
    port(clk , CLR : in std_logic; 
    Q : out std_logic_vector(2 downto 0));  
end counter; 

architecture archi of counter is 

    signal tmp: std_logic_vector(2 downto 0); 

    begin  
    process (clk, CLR) 
     begin  

     if (CLR='1') then     
      tmp <= "000";      
     elsif (clk'event and clk='1') then 
       tmp <= tmp + 1;      
      end if;   

    end process; 

    Q <= tmp; 

end archi; 

---

這是解碼器的程序：

library IEEE; 

use IEEE.std_logic_1164.all; 

entity led_inp is 

    port (I : in std_logic_vector(2 downto 0) ; 

    L : out std_logic_vector(6 downto 0)) ; 

end led_inp ; 

architecture led_inp1 of led_inp is 

Begin  
    L(0) <= (not I(0)) and (not I(1)) and (not I(2)); 
    L(1) <= (not I(0)) and (not I(1)) and I(2); 
    L(2) <= (not I(0)) and I(1) and (not I(2)); 
    L(3) <= (not I(0)) and I(1) and I(2); 
    L(4) <= I(0) and (not I(1)) and (not I(2)); 
    L(5) <= I(0) and (not I(1)) and I(2); 
    L(6) <= I(0) and I(1) and (not I(2)); 
end led_inp1; 

---

這是整個設計的結構形式：

library IEEE; 

use IEEE.std_logic_1164.all; 

-- the entity of the whole design block, here i have given the names of the ports as the ones which i have used in my individual components 

entity led_design is 
    port(clock,CLEAR :in std_logic;   
    L :out std_logic_vector(6 downto 0)); 
end led_design; 

architecture led_design1 of led_design is 
-- declaring my counter as a component 
    component counter 
    port(clk, CLR : in std_logic;  
    Q : out std_logic_vector(2 downto 0)); 
end component ; 

-- declaring my decoder as a component 

component led_inp 
    port (I : in std_logic_vector(2 downto 0) ; 
    L : out std_logic_vector(6 downto 0)) ; 
end component ; 

signal I:std_logic_vector(2 downto 0); 
begin 
    -- The PORT MAPPING BEGINS 

    L1: counter port map(clk=>clock,CLR=>CLEAR,I(2)=>I(2),I(1)=>I(1),I(0)=>I(0)); 

    L2: led_inp port map(I(2)=>I(2),I(1)=>I(1),I(0)=>I(0),L(0)=>L(0),L(1)=>L(1),L(2)=>L(2),L(3)=>L(3),L(4)=>L(4),L(5)=>L(5),L(6)=>L(6)); 

    L1: counter port 

    map(clk=>clock,CLR=>CLEAR,I(2)=>h(2),I(1)=>h(1),I(0)=>h(0)); 
end led_design1; 

這是其自帶的錯誤了：ERROR
ncvhdl_p：* E，FMLBAD（led_count，85 | 44）：元素協會87 [4.3.3.2] 93 [4.3.2.2]的形式不完整。 錯誤：1，警告：0"

Answer 1

注意符號led_count不會在你的VHDL設計描述露面，是文件名

你有兩個標籤L1在led_design？ ，它也缺少信號h與信號I匹配的聲明（它也告訴你它沒有在其他地方使用）。

兩個counter關聯列表（端口映射）與組件聲明不匹配。你的代碼分析的東西。注意h不在其他地方使用。

閱讀Markdown help以瞭解如何格式化代碼，這很糟糕。

缺乏正確的格式和無法理解錯誤是阻止那些可以從提供答案中回答的人。

試試這個：

library IEEE; 
use IEEE.std_logic_1164.all; 
--use IEEE.std_logic_unsigned.all; 
use ieee.numeric_std.all; 

entity counter is 
    port(clk , CLR : in std_logic;  
     Q : out std_logic_vector(2 downto 0)); 
end counter; 

architecture archi of counter is 

    signal tmp: std_logic_vector(2 downto 0); 

begin 

    process (clk, CLR) 
    begin  

     if (CLR='1') then     
      tmp <= "000";   
     elsif (clk'event and clk='1') then  
      tmp <= std_logic_vector(unsigned(tmp) + 1);    
     end if;   

    end process; 

    Q <= tmp; 

end archi; 



library IEEE; 
use IEEE.std_logic_1164.all; 

entity led_inp is 
    port (I : in std_logic_vector(2 downto 0) ; 
      L : out std_logic_vector(6 downto 0)) ; 
end led_inp ; 

architecture led_inp1 of led_inp is 

Begin 

    L(0) <= (not I(0)) and (not I(1)) and (not I(2)); 
    L(1) <= (not I(0)) and (not I(1)) and I(2); 
    L(2) <= (not I(0)) and I(1) and (not I(2)); 
    L(3) <= (not I(0)) and I(1) and I(2); 
    L(4) <= I(0) and (not I(1)) and (not I(2)); 
    L(5) <= I(0) and (not I(1)) and I(2); 
    L(6) <= I(0) and I(1) and (not I(2)); 

end led_inp1; 



library IEEE; 
use IEEE.std_logic_1164.all; 

entity led_design is 
    port(clock,CLEAR :in std_logic;  
      L :out std_logic_vector(6 downto 0)); 
end led_design; 

architecture led_design1 of led_design is 

    component counter 
     port(clk, CLR : in std_logic;  
      Q : out std_logic_vector(2 downto 0)); 
    end component ; 

    component led_inp 
     port (I : in std_logic_vector(2 downto 0) ; 
       L : out std_logic_vector(6 downto 0)) ; 
    end component ; 

    signal I:std_logic_vector(2 downto 0); 
    signal h:std_logic_vector(2 downto 0); 
begin 

L1: counter port map (
     clk=>clock,CLR=>CLEAR, Q => I); -- I(2)=>I(2),I(1)=>I(1),I(0)=>I(0)); 

L2: led_inp port map (I(2)=>I(2),I(1)=>I(1),I(0)=>I(0),L(0)=>L(0),L(1)=>L(1),L(2)=>L(2),L(3)=>L(3),L(4)=>L(4),L(5)=>L(5),L(6)=>L(6)); 

L3: counter port map(clk=>clock,CLR=>CLEAR, Q => h);-- I(2)=>h(2),I(1)=>h(1),I(0)=>h(0)); 
-- ERROR 
--**ncvhdl_p: *E,FMLBAD (led_count,85|44): poorly formed formal part of element association 87[4.3.3.2] 93[4.3.2.2]. 
-- errors: 1, warnings: 0"** 


end led_design1; 

爲numeric_std和類型轉換的使用條款是爲了讓我使用-1993兼容工具（不具有std_logic_unsigned）。您的環境中可能不需要這些更改。

注意現在標記爲L3的第二個計數器（連接到h）的輸出不會去任何地方。

意識到錯誤也應該在83行顯示，如果你只是修復線85