VHDL設置RAM中的常量數據

Question

最近我使用VHDL編寫一個16-RAM的RAM。我的代碼是：

library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 
use IEEE.STD_LOGIC_ARITH.ALL; 
use IEEE.STD_LOGIC_UNSIGNED.ALL; 
use IEEE.Numeric_Std.all; 

entity RAM is 
port(
PC_in: in std_logic_vector (5 downto 0); 
EN_WR_in: in std_logic_vector (1 downto 0); 
RAM_in : in std_logic_vector(15 downto 0); 
RAM_out : out std_logic_vector(15 downto 0); 
test : out integer 
); 


end RAM; 

architecture Behavioral of RAM is 
type ram_t is array (63 downto 0) of std_logic_vector(15 downto 0); 
signal ram : ram_t; 
begin 
PROCESS (EN_WR_in) 
BEGIN 
     if (EN_WR_in(1)='1') then 

     IF (EN_WR_in(0) = '1') THEN 
      ram(conv_integer(unsigned(PC_in))) <= RAM_in; 
      else 
     RAM_out <= ram(conv_integer(unsigned(PC_in))); 
     end if; 

     else 

     RAM_out <="ZZZZZZZZZZZZZZZZ"; 

     end if; 

END PROCESS; 
    ram(20) <= "0000100010010000"; 
end Behavioral; 

，我與面臨的問題是我需要設置在RAM中的一些常量數據就像

ram(20) <= "0000100010010000"; 

但恆定的數據模擬過程中並不存在。有什麼辦法解決它？

謝謝。

Answer 1

在聲明它可以初始化RAM：

signal ram : ram_t := ("0000100010010000", x"1234", ...); 

或許

signal ram : ram_t := (20 => "0000100010010000", others => (others=>'0'));