索引在堪薩斯熔岩信號矩陣矩陣

Question

我試圖實現時間複用驅動7位數字顯示4位數：設備有7個數據腿和4個陽極，所以如果你想顯示四不同的數字，您必須首先將陽極設置爲0001，並將數據分支設置爲段;然後過一會兒，將陽極設置爲0010並更新數據支路;等等。

我正試圖在堪薩斯熔岩中實現這個。但是，Xilinx編譯器會拒絕生成的VHDL，並且會出現類型錯誤（並查看生成的代碼，我認爲這是正確的）。首先，我的Lava代碼：它基本上實現了序列[0, 1, 2, 3, 0, ...]的信號，然後使用Language.KansasLava.Signal中的.!.運算符來索引矩陣矩陣參數。陽極值是通過在每個時步向左旋轉0001生成的。

{-# LANGUAGE TypeFamilies #-} 
{-# LANGUAGE ScopedTypeVariables #-} 
{-# LANGUAGE DataKinds #-} 
import Language.KansasLava 
import Hardware.KansasLava.Boards.Papilio.LogicStart -- from http://github.com/gergoerdi/kansas-lava-papilio 
import Data.Sized.Matrix 
import Data.Sized.Unsigned as Unsigned 
import Data.Bits 

driveSS :: forall clk sig n. (Clock clk, sig ~ Signal clk, Size n, Rep n, Num n, Integral n) => Matrix n (Matrix X7 (sig Bool)) -> SevenSeg clk ActiveLow n 
driveSS segss = SevenSeg (fmap bitNot anodes) segs high 
    where 
    clkAnode :: sig Bool 
    clkAnode = divideClk (Witness :: Witness X8) 

    selector :: sig n 
    selector = counter clkAnode 

    segss' :: sig (Matrix n (Matrix X7 Bool)) 
    segss' = pack . fmap pack $ segss 

    segs :: Matrix X7 (sig Bool) 
    segs = unpack $ segss' .!. selector 

    anodes :: Matrix n (sig Bool) 
    anodes = rotatorL clkAnode 

test_sseg :: Fabric() 
test_sseg = do 
    sw <- switches 
    let sw' = cropAt sw 1 
    sseg $ driveSS $ matrix [sw', zero, zero, zero] 
    where 
    zero = matrix $ replicate 7 low 

divideClk :: forall c sig ix. (Clock c, sig ~ Signal c, Size ix) => Witness ix -> sig Bool 
divideClk _ = counter high .==. (0 :: sig (Unsigned ix)) 

counter :: (Rep a, Num a, Clock c, sig ~ Signal c) => sig Bool -> sig a 
counter inc = loop 
    where 
    reg = register 0 loop 
    loop = mux inc (reg, reg + 1) 

rotatorL :: (Clock c, sig ~ Signal c, Size ix, Integral ix) => sig Bool -> Matrix ix (sig Bool) 
rotatorL step = fromUnsigned loop 
    where 
    reg = register 1 loop 
    loop = mux step (reg, rotateL reg 1) 

fromUnsigned :: (sig ~ Signal c, Size ix) => sig (Unsigned ix) -> Matrix ix (sig Bool) 
fromUnsigned = unpack . coerce Unsigned.toMatrix 

main :: IO() 
main = do 
    writeVhdlPrelude "lava-prelude.vhdl" 
    kleg <- reifyFabric $ do 
     board_init 
     test_sseg 
    writeVhdlCircuit "hello" "hello.vhdl" kleg 
    writeUCF "hello.ucf" kleg 

所以，當我嘗試編譯生成VHDL，我收到此錯誤信息：

ERROR:HDLParsers:800 - "/home/cactus/prog/lava/hello/src/hello.vhdl" Line 85. Type of sig_24_o0 is incompatible with type of sig_28_o0. 

從hello.vhdl相關的線路有：

type sig_24_o0_type is array (7 downto 0) of std_logic_vector(0 downto 0); 
signal sig_24_o0 : sig_24_o0_type; 

signal sig_25_o0 : std_logic_vector(1 downto 0); 

type sig_28_o0_type is array (3 downto 0) of std_logic_vector(6 downto 0); 
signal sig_28_o0 : sig_28_o0_type; 

sig_24_o0 <= sig_28_o0(to_integer(unsigned(sig_25_o0))); 

類型的sig_24_o0似乎是錯誤的;我認爲它應該是array (6 downto 0) of std_logic_vector(0 downto 0)或std_logic_vector(6 downto 0)，但我不知道Lava使用那些std_logic_vector(0 downto 0)的。

Answer 1

我結束瞭解決此整個總線工作通過復每線，而不是複用：使用輔助函數

nary :: forall a clk sig n. (Clock clk, sig ~ Signal clk, Rep a, Size n, Rep n) => sig n -> Matrix n (sig a) -> sig a 
nary sel inps = pack inps .!. sel 

這樣產生的VHDL編譯就好

segss' :: Matrix X7 (Matrix n (sig Bool)) 
segss' = columns . joinRows $ segss 

segs :: Matrix X7 (sig Bool) 
segs = fmap (nary selector) segss' 

;儘管我不知道它是否會導致更復雜的電路（或者甚至更簡單）。