Verilog註冊碼錯誤 - 條件檢查

Question

我正在測試一個8位寄存器的模塊，與我的其餘代碼分開。我使用ModelSim來設置值，然後運行以查看結果。 該模塊應該有一個二進制數字輸入，一個清除位，一個使能位和一個輸出。

module Register8bit(D, Clk, Clear, Enable, OutNum); 
    input [7:0] D; //8 bit binary data 
    input Clk;  //Clock 
    input Clear;  //Clear bit 
    input Enable; //Enable bit 
    output reg [7:0] OutNum; 

always @(posedge Clk) 
begin 
    if (Enable) 
     begin 
      if (Clear) 
       OutNum <= 8'b00000000; 
      else 
       OutNum <= D; 
     end 
end 
endmodule 

這裏是我期望的輸出（以該順序），以d = 10001111和CLK = 1

Steps CLR Enable OutNum 
1  0  0   xxxxxxxx (initially undefined) 
2  0  1   10001111 (input data is used) 
3  1  0   10001111 (because write-protection) 
4  1  1   00000000 (Clear and Enable are true, so set to 0) 
5  0  1   10001111 (Clear is false and Enable is true, so use input data) 

第一步作品，但第二個不（所以休息也不工作）。具體而言，OutNum在第二步中保持未定義狀態。如果啓用爲true，則使用輸入數據更新OutNum將在第一步中起作用。

我應該如何修復這個模塊？

測試臺代碼：

`timescale 1ns/1ps 

module test_register; 

//inputs 
reg [7:0] D; 
reg Clk; 
reg Clear; 
reg Enable; 

//outputs 
reg [7:0] OutNum; 

//instantiate 
Register8bit uut(
    .D(D), 
    .Clk(Clk), 
    .Clear(Clear), 
    .Enable(Enable) 
); 

initial begin 
    D = 10001111; 
    Clk = 1; 

    //step 1 
    #100; 
    Clear = 0; 
    Enable = 0; 
    #100; 

    //step 2 
    Clear = 0; 
    Enable = 1; 
    #100; 

    //step 3 
    Clear = 1; 
    Enable = 0; 
    #100; 

    //step 4 
    Clear = 1; 
    Enable = 1; 
    #100; 

    //step 5 
    Clear = 0; 
    Enable = 1; 
    #100; 
end 
endmodule 

Answer 1

你需要切換您Clk信號多次。你的代碼只是將它設置爲1，然後將它留在1整個模擬。

module test_register; 

//inputs 
reg [7:0] D; 
reg Clk; 
reg Clear; 
reg Enable; 

//outputs 
reg [7:0] OutNum; 

//instantiate 
Register8bit uut(
    .OutNum (OutNum), // <---- added missing output 
    .D(D), 
    .Clk(Clk), 
    .Clear(Clear), 
    .Enable(Enable) 
); 

always #50 Clk = ~Clk; 

always @(negedge Clk) begin 
    $display($time, " clr=%b en=%b D=%b OutNum=%b", Clear, Enable, D, OutNum); 
end 

initial begin 
    D = 'b10001111; // <---- use 'b 
    Clk = 1; 

    #50; 

    //step 1 
    #100; 
    Clear = 0; 
    Enable = 0; 
    #100; 

    //step 2 
    Clear = 0; 
    Enable = 1; 
    #100; 

    //step 3 
    Clear = 1; 
    Enable = 0; 
    #100; 

    //step 4 
    Clear = 1; 
    Enable = 1; 
    #100; 

    //step 5 
    Clear = 0; 
    Enable = 1; 
    #100; 
    #500 $finish; 
end 
endmodule 

/* 

Prints out: 

        50 clr=x en=x D=10001111 OutNum=xxxxxxxx 
       150 clr=0 en=0 D=10001111 OutNum=xxxxxxxx 
       250 clr=0 en=1 D=10001111 OutNum=xxxxxxxx 
       350 clr=1 en=0 D=10001111 OutNum=10001111 
       450 clr=1 en=1 D=10001111 OutNum=10001111 
       550 clr=0 en=1 D=10001111 OutNum=00000000 
       650 clr=0 en=1 D=10001111 OutNum=10001111 
       750 clr=0 en=1 D=10001111 OutNum=10001111 
       850 clr=0 en=1 D=10001111 OutNum=10001111 
       950 clr=0 en=1 D=10001111 OutNum=10001111 
       1050 clr=0 en=1 D=10001111 OutNum=10001111 

*/