2017-11-18 194 views
-1

我不明白爲什麼我在使用model-sim時出現此錯誤,我嘗試了很多修復程序,但似乎無法解決此問題。錯誤:(vsim -3389),

這是我的ModelSim成績單說什麼:

** Error: (vsim-3389) C:/Users/VRN/Desktop/sha256/t_processing.v(31): Port 'a_in' not found in the connected module (5th connection).

# Time: 0 ps Iteration: 0 Instance: /t_processing/uut File: C:/Users/VRN/Desktop/sha256/interative_processing.v

7與輸入端口

`timescale 1ns/1ps 


module interative_processing(clk,rst,w,k,counter_iteration,padding_done,a_out,b_out,c_out,d_out,e_out,f_out,g_out,h_out 

    ); 

    input clk,rst,padding_done; 
    input [6:0] counter_iteration; 
    input [31:0] w,k; 

    output reg [31:0] a_out,b_out,c_out,d_out,e_out,f_out,g_out,h_out; 

    reg temp_case,temp_if; 
    reg [31:0] a_temp,b_temp,c_temp,d_temp,e_temp,f_temp,g_temp,h_temp; 
    reg [31:0] semation_0,semation_1,ch,maj; 

    [email protected](posedge clk) 
    begin 
    if(rst==0) 
    begin 
      temp_case=1'b0; 
      a_out=32'h6a09e667; 
      b_out=32'hbb67ae85; 
      c_out=32'h3c6ef372; 
      d_out=32'ha54ff53a; 
      e_out=32'h510e527f; 
      f_out=32'h9b05688c; 
      g_out=32'h1f83d9ab; 
      h_out=32'h5be0cd19; 
    end 
    else 
    begin 

      semation_0=({a_out[1:0],a_out[31:2]})^({a_out[12:0],a_out[31:13]})^({a_out[21:0],a_out[31:22]}); //last 22 ROTR22 
      semation_1=({e_out[5:0],e_out[31:6]})^({e_out[10:0],e_out[31:11]})^({e_out[24:0],e_out[31:25]}); 

      maj=(a_out & b_out)^(a_out & c_out)^(b_out & c_out); 
      ch=(e_out & f_out)^(~e_out & g_out); 
      if(counter_iteration==65) 
      begin 
      a_out=a_out; 
      b_out=b_out; 
      c_out=c_out; 
      d_out=d_out; 
      e_out=e_out; 
      f_out=f_out; 
      g_out=g_out; 
      h_out=h_out; 
      end 
      else 
      begin 

      if(padding_done==1) 
      begin 
      case(temp_case) 
      1'b0: temp_case=1'b1; 
      1'b1: temp_if=1'b1; 
      endcase 
      end 

      if(temp_if==1 && counter_iteration!=64) 
      begin 
      a_temp= h_out + semation_1 + ch + k + w + semation_0 + maj;  // T2= semation_0 + maj(a,b,c); 
      b_temp= a_out; 
      c_temp= b_out; 
      d_temp= c_out; 
      e_temp= d_out + h_out + semation_1 + ch + k + w;  //T1 = h_out + semation_1 + ch + k + w; 
      f_temp= e_out; 
      g_temp= f_out; 
      h_temp= g_out; 

      a_out=a_temp; 
      b_out=b_temp; 
      c_out=c_temp; 
      d_out=d_temp; //alternative of non-blocking though 
      e_out=e_temp; 
      f_out=f_temp; 
      g_out=g_temp; 
      h_out=h_temp; 

      end 
      end 
    end 

    end 

endmodule 

和我的測試平臺類似的錯誤:

`timescale 1ns/1ps 

module t_processing; 

    // Inputs 
    reg clk; 
    reg rst; 
    reg [31:0] w; 
    reg [31:0] k; 
    reg [31:0] a_in; 
    reg [31:0] b_in; 
    reg [31:0] c_in; 
    reg [31:0] d_in; 
    reg [31:0] e_in; 
    reg [31:0] f_in; 
    reg [31:0] g_in; 
    reg [31:0] h_in; 

    // Outputs 
    wire [31:0] a_out; 
    wire [31:0] b_out; 
    wire [31:0] c_out; 
    wire [31:0] d_out; 
    wire [31:0] e_out; 
    wire [31:0] f_out; 
    wire [31:0] g_out; 
    wire [31:0] h_out; 

    // Instantiate the Unit Under Test (UUT) 
    interative_processing uut (
     .clk(clk), 
     .rst(rst), 
     .w(w), 
     .k(k), 
     .a_in(a_in), 
     .b_in(b_in), 
     .c_in(c_in), 
     .d_in(d_in), 
     .e_in(e_in), 
     .f_in(f_in), 
     .g_in(g_in), 
     .h_in(h_in), 
     .a_out(a_out), 
     .b_out(b_out), 
     .c_out(c_out), 
     .d_out(d_out), 
     .e_out(e_out), 
     .f_out(f_out), 
     .g_out(g_out), 
     .h_out(h_out) 
    ); 

    initial begin 
     // Initialize Inputs 
     clk = 0; 
     rst = 0; 
     w = 0; 
     k = 0; 
     a_in = 0; 
     b_in = 0; 
     c_in = 0; 
     d_in = 0; 
     e_in = 0; 
     f_in = 0; 
     g_in = 0; 
     h_in = 0; 

     end 

    initial 
    begin // Wait 100 ns for global reset to finish 
     #100; 
    end 

      initial clk=1'b0; 
    always @(clk) clk<= #5 ~clk; 

    initial 
    begin 
     rst = 1'b0; 
     #10 rst = 1'b1; 
     k = 32'hc67178f2; 
     w = 32'h12b1edeb; 
     a_in = 32'hd39a2165; 
     c_in = 32'hb85e2ce9; 
     d_in = 32'hb6ae8fff; 
     e_in = 32'hfb121210; 
     f_in = 32'h948d25b6; 
     g_in = 32'h961f4894; 
     h_in = 32'hb21bad3d; 
     b_in= 32'h04d24d6c; 
    end 

endmodule 
+0

太。許多。碼。 Google MCVE。 – toolic

+0

這是沒有意義的:'初始 開始//等待100納秒全局復位完成 #100; end'它不會等待任何事情。該塊將與所有其他塊並行執行,因爲#100之後沒有代碼,它不會執行任何操作。 – Serge

+0

錯誤信息如何不夠清楚?模塊'interative_processing'沒有輸入調用'a_in',但你試圖在測試平臺上連接它。 – Greg

回答

1

這裏的輸入列表/輸出端口在interactive_processing模塊中定義。

input wire  clk, 
input wire  rst, 
input wire  padding_done; 
input wire [6:0] counter_iteration; 
input wire [31:0] w, 
input wire [31:0] k, 
output reg [31:0] a_out, 
output reg [31:0] b_out, 
output reg [31:0] c_out, 
output reg [31:0] d_out, 
output reg [31:0] e_out, 
output reg [31:0] f_out, 
output reg [31:0] g_out, 
output reg [31:0] h_out 

下面是您嘗試傳遞給interactive_processing模塊的輸入和輸出的列表。

.clk(clk), 
.rst(rst), 
.w(w), 
.k(k), 
.a_in(a_in), 
.b_in(b_in), 
.c_in(c_in), 
.d_in(d_in), 
.e_in(e_in), 
.f_in(f_in), 
.g_in(g_in), 
.h_in(h_in), 
.a_out(a_out), 
.b_out(b_out), 
.c_out(c_out), 
.d_out(d_out), 
.e_out(e_out), 
.f_out(f_out), 
.g_out(g_out), 
.h_out(h_out) 

編譯器有不知道該怎麼過h__ina__in因爲你不是他們定義爲輸入到模塊。