如何初始化std_logic_vector？

Question

我有這樣的代碼

--RAM module 
library IEEE; 
use IEEE.STD_LOGIC_1164.all; 
use IEEE.numeric_std.all; 

entity RAM is 
    generic(
    address_length, data_length : integer); 
    port(
    addr  : in std_logic_vector(address_length-1 downto 0); 
    dat  : inout std_logic_vector(data_length-1 downto 0); 
    rd, wr, en : in bit); 
end entity RAM; 

architecture RAM_impl of RAM is 
    type mem is array(2**address_length-1 downto 0) of std_logic_vector(data_length-1 downto 0); 
begin 
    process(rd, wr, en)is 
    variable cont : mem; 
    begin 
    if(en = '1')then 
     if(wr = '1' and rd = '0')then 
     cont(to_integer(unsigned(addr))) := dat; 
     end if; 
     if(rd = '1' and wr = '0')then 
     dat <= cont(to_integer(unsigned(addr))); 
     end if; 
    end if; 
    end process; 
end architecture RAM_impl; 


--Test module 
library IEEE; 
use IEEE.STD_LOGIC_1164.all; 
use IEEE.numeric_std.all; 

entity Example4RAM is 
end entity Example4RAM; 

architecture Tester of Example4RAM is 
    signal rd, wr, en : bit; 
    signal str  : std_logic_vector(15 downto 0); 
    signal ext  : std_logic_vector(7 downto 0); 
begin 
    module : entity work.RAM(RAM_impl) 
    generic map(
     address_length => 16, 
     data_length => 8) 
    port map(str, ext, rd, wr, en); 
    tt : process is 
    begin 
    str <= X"0001"; 
    ext <= "00000000"; 
    rd <= '0'; wr <= '1'; 
    wait for 5 ns; 
    en <= '1'; 
    wait for 5 ns; 
    rd <= '0'; wr <= '0'; 
    wait for 10 ns; 
    rd <= '1'; wr <= '0'; 
    end process; 
end architecture Tester; 

當我運行該內存模塊海峽矢量模擬初始化不錯，但內線矢量保持初始化。在RAM模塊中，str是在向量中，而ext是在向量中。這是以某種方式造成問題，有誰知道解決方案？ （我從昨天開始改變源代碼，但它仍然不能工作）

Answer 1

我添加了一個RAM模塊，並稍微修改了測試激勵（當wr變爲無效時，ext被驅動到所有的'Z'（行爲模型不需要保持。以上）

library ieee; 
use ieee.std_logic_1164.all; 
use ieee.numeric_std.all; 

entity RAM is 
    generic (
     constant address_length: natural := 16; 
     constant data_length:  natural := 8 
    ); 
    port (
     signal str:  in  std_logic_vector (address_length-1 downto 0); 
     signal ext:  inout std_logic_vector (data_length-1 downto 0); 
     signal rd:  in  BIT; 
     signal wr:  in  BIT 
    ); 
end entity; 

architecture RAM_impl of RAM is 
    type ram_array is array (natural range address_length-1 downto 0) 
     of std_logic_vector (data_length-1 downto 0); 
    signal mem_array: ram_array; 
begin 


MEMORY: 
    process (str, ext, rd, wr) 
     variable addr: natural range 0 to 2**address_length -1 ; 
    begin 
     addr := TO_INTEGER(UNSIGNED(str)); -- heed the warnings 
     if wr = '1' then 
      mem_array(addr) <= ext; 
     end if; 
     if rd = '0' then 
      ext <= (others => 'Z'); 
     else 
      ext <= mem_array(addr); 
     end if; 
    end process; 


end architecture; 

library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 
-- use IEEE.numeric_std.ALL; 

entity Example4RAM is 
end entity Example4RAM; 

architecture Tester of Example4RAM is 
signal rd,wr,clk: bit; 
signal str: std_logic_vector(15 downto 0); 
signal ext: std_logic_vector(7 downto 0); 
begin 

module: 
    entity work.RAM(RAM_impl) 
     generic map (
      address_length=>16, 
      data_length=>8 
     ) 
     port map (
      str, 
      ext, 
      rd, 
      wr 
     ) 
    ; 

tt: 
    process 
    begin 
     str<=X"0001"; 
     ext<="00000000"; 
     wait for 5 ns; 
     rd<='0';wr<='1'; 
     wait for 5 ns; 
     rd<='0';wr<='0'; 
     ext <= (others => 'Z'); -- ADDED 
     wait for 10 ns; 
     rd<='1';wr<='0'; 
     wait for 20 ns; -- ADDED 
     str <=X"0002"; -- ADDED 
     wait for 20 ns; -- ADDED 
     wait; 
    end process; 
end architecture Tester; 

對刺激的改變包括改變表示RAM地址讀取一個未初始化的位置返回「U的（在波形UU）：

ghdl -a exampleram.vhdl 
ghdl -r Example4RAM --wave=Example4RAM.ghw 
../../../../libraries/ieee/numeric_std-body.v93:2098:7:@0ms:(assertion warning): 
NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 
open *.ghw 

實質上，當任何一個人不應該驅動一個值時，該進程和RAM驅動器將與所有'Z'分機。在讀取之前寫入從str地址X「0001」隱藏'U'值。如您所見，如果地址更改爲未初始化的位置，則顯示「U」。分辨率傳遞RAM讀取數據或向雙向數據總線（ext）上的RAM陣列提供寫入數據。 （這是在帶有ghdl mcode版本的Mac上完成的（直接編譯，就像Windows一樣，不需要明確的闡述），並使用GTKWave顯示）。

斷言警告（檢測到的元值）來自在零時間（@ 0ms）分配給str（所有'U'）的默認值。