VHDL音序器：遞增FSM中的輸出信號

Question

我正在使用音序器，我無法弄清楚如何遞增一些輸出信號。在狀態1（S1）我想增加ram_add_wr（在每個時鐘週期）。

clocked_process:PROCESS(clk,rst) 
    VARIABLE count: INTEGER RANGE 0 TO 32; 
BEGIN 
     IF (rst = '0') THEN 
      pr_state <= idle; 
      count := 0; 
     ELSIF (clk'event AND clk='1') THEN  
      count := count+1; 
      IF (count>=timer) THEN 
       pr_state <= nx_state; 
       count := 0; 
      END IF; 
     END IF; 
END PROCESS;   

PROCESS(pr_state, en) 
BEGIN   
    CASE pr_state IS 
     WHEN idle => 
     timer <= 1; 
      IF (en = '1') THEN 
       sig_ram_add_wr <= "00000"; 
       nx_state <= s1; 
      ELSE 
       nx_state <= idle; 
       sig_ram_add_wr <= "00000"; 
    END IF; 

     WHEN s1 =>   
     timer <= 32; 
      IF (en ='1') THEN 
     --timer <= 1; 

Answer 1

您可以使用兩個計數器寄存器。

... 
    signal cntReg, cntReg_next: integer range 0 to 31 := 0; 

begin 

    -- Clocked process -- 
    ... 
    elsif (clk'event and clk='1') then 
     if (pr_state = s1) then 
      cntReg <= cntReg_next; 
     end if; 
     ... 
    ... 


    -- Combined process -- 
    ... 
    when s1 => 
     cntReg_next <= cntReg + 1; 
    ... 

    -- output (depends on the type of sig_ram_add_wr) 
    sig_ram_add_wr <= std_logic_vector(to_unsigned(cntReg, 5)); 

在其他國家，你需要在兩個cntReg和cntReg_next重置爲0。

Answer 2

無需單獨的進程 - 做這樣的事情：

clocked_process:PROCESS(clk,rst) 

    VARIABLE count: INTEGER RANGE 0 TO 32; 
    variable addr : unsigned(sig_ram_add_wr'range); 
BEGIN 

     IF rst = '0' THEN 
      ... 
      addr := (others => '0'; 
     ELSIF rising_edge(clk) THEN  
      ... 
      if pr_state = s1 then 
      addr := addr + 1; -- update the address counter here 
      end if; 
      ... 
     END IF; 
     sig_ram_add_wr <= std_logic_vector(addr); -- copy it onto the output pins here - as this is outside the clocked element, the synthesiser will just create a wire 
END PROCESS;   

其他說明：

• 無需圍繞您的if條件的括號
• 如果rst將是低有效，我將指示在信號/引腳名稱（I通常使用_n後綴，所以rst_n