如何消除vhdl Adder的信號？

我寫了下面的VHDL代碼，它是快速加法器的組成部分。快速加法器由一個8by8寄存器組成，該寄存器連接到代碼如下的加法器。我如何消除在Read_Adress中的使用。我想要Read_Adress出std_logic_vector不inout？如何消除vhdl Adder的信號？

library ieee; 
use ieee.std_logic_1164.all; 
use ieee.numeric_std.all; 
use ieee.std_logic_unsigned.all; 

Entity Adder is 
port(
     Clock_50_MHZ :in std_logic; 
     En :in std_logic; 
     Data_Registerfile : in std_logic_vector(7 downto 0); 
     Read_Address: inout std_logic_vector(2 downto 0) := "000"; 
      Output : out std_logic_vector(11 downto 0) 
); 
end Adder; 

Architecture arch of Adder is 
Signal result : unsigned (11 downto 0):="000000000000"; 
Signal regData: std_logic_vector(7 downto 0); 

Begin 
regData <= Data_Registerfile; 
Process(Clock_50_MHZ) 
Begin 
if rising_edge(Clock_50_MHZ) then 
    if (En = '1') then 
     if(Read_Address = "000") then 
      result <= "000000000000" + unsigned(regData); 
      Read_Address <= Read_Address + 1; 
     elsif(Read_Address = "111") then 
      Output <= std_logic_vector(result + unsigned(regData)); 
      Read_Address <= "000"; 
     else 
      result <= result + unsigned(regData); 
      Read_Address <= Read_Address + 1; 
     end if; 
    end if; 
end if; 
End Process; 
end arch;

來源

2012-10-19 Ivan

這是VHDL經典的不便：你不能使用你的out端口爲信號（如果你使用的Verilog，你經常會發現自己想要做這一點）。

，我知道的最好的方法是創建一個額外的虛擬信號：

signal Read_Address_tmp : std_logic_vector(2 downto 0) := "000";

做的計算與：

 Process(Clock_50_MHZ) 
Begin 
if rising_edge(Clock_50_MHZ) then 
    if (En = '1') then 
     if(Read_Address_tmp = "000") then 
      result <= "000000000000" + unsigned(regData); 
      Read_Address_tmp <= Read_Address_tmp + 1; 
     elsif(Read_Address_tmp = "111") then 
      Output <= std_logic_vector(result + unsigned(regData)); 
      Read_Address_tmp <= "000"; 
     else 
      result <= result + unsigned(regData); 
      Read_Address_tmp <= Read_Address_tmp + 1; 
     end if; 
    end if; 
end if; 
    End Process;

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