以下代碼是一個4:1多路複用器。如果dis
信號爲'1',則所有輸出引腳的輸出應爲0。有沒有一個簡明的方式來表明,如果dis
是高的,那麼輸出應該是0,無論sel
,沒有 必須通過sel
的每個組合排列?VHDL:條件信號分配的簡明表述
我知道,在某些情況下,如果條件分配模糊不清,則可能會出現無意識的鎖存器生成以及其他不良的副作用。
architecture dataflow of mux8_4 is
begin
q <=d0 when sel = "00" and dis = '0' else
d1 when sel = "01" and dis = '0' else
d2 when sel = "10" and dis = '0' else
d3 when sel = "11" and dis = '0' else
"00000000" when sel = "00" and dis = '1' else
"00000000" when sel = "01" and dis = '1' else
"00000000" when sel = "10" and dis = '1' else
"00000000" when sel = "11" and dis = '1';
end architecture dataflow;
我嘗試(我瞭解所有可能的語句的遺漏是壞 ,但實際上)
architecture dataflow of mux8_4 is
begin
q <= "00000000" when dis = '1' else
d0 when sel = "00" and dis = '0' else
d1 when sel = "01" and dis = '0' else
d2 when sel = "10" and dis = '0' else
d3 when sel = "11" and dis = '0';
end architecture dataflow;