Verilog：3D可合成參數

Question

是否可以在Verilog中創建可合成的3D參數？

我想要做類似該C代碼風格的東西：

parameter [8][5]test [5] = { 
{ 
{0, 1, 2, 3, 4}, 
{5, 6, 7, 8, 9}, 
{10, 11, 12, 13, 14}, 
{15, 16, 17, 18, 19}, 
{20, 21, 22, 23, 24} 
},{ 
{4, 3, 2, 1, 0}, 
{9, 8, 7, 6, 5}, 
{14, 13, 12, 11, 10}, 
{19, 18, 17, 16, 15}, 
{24, 23, 22, 21, 20} 
}... 
} 

Answer 1

的Verilog不允許參數數組，所以你的運氣了。 SystemVerilog的確如此。