在帶有時鐘分頻器和不同輸出的verilog上實現testbench

Question

對於下面的代碼，這是一個7段59秒計數器，我試圖實現一個測試臺。我遇到了兩個問題：一個是我用實際時鐘q [24]來計算近似秒數，但在測試平臺中，我應該能夠看到不同的輸出，而不需要實現數千個時鐘。另一個麻煩是，我想在測試臺中看到寄存器[3：0] unidad和[3：0] decena中的輸出，它們是7段面板上的每個數字，但是在代碼中沒有使用如輸入或輸出，但作爲實習變量。

我怎麼能實現這樣一個模擬，在合理的時間內顯示死亡/單身輸出？謝謝。

module cont(
    input clock, 
    input reset, 
    output reg [6:0]segm, 
    output [3:0]an 
    ); 

reg [3:0]unidad; 
reg [3:0]decena; 

reg [24:0] q; 

always @(posedge clock or posedge reset) 
    begin 
     if(reset == 1) 
     q <= 0; 
     else 
      q <= q + 1; 
    end 

always @ (posedge q[24] or posedge reset) 
begin 
    if (reset) begin 
    unidad <= 0; 
    decena <= 0; 
    end 
    else if (unidad==4'd9) 
    begin 
    unidad <= 0; 
    if (decena==4'd5) 
     decena <= 0; 
     else 
     decena <= decena + 1; 
    end 
    else 
    unidad <= unidad + 1; 
    end 

reg [6:0]sseg; 
reg [3:0]an_temp; 
always @ (*) 
begin 
    case(q[13]) 

    1'b0 : 
    begin 
    sseg = unidad; 
    an_temp = 4'b1110; 
    end 

    1'b1 : 
    begin 
    sseg = decena; 
    an_temp = 4'b1101; 
    end 

    endcase 
end 
assign an = an_temp; 

always @ (*) 
begin 
    case(sseg) 
    4'd0 : segm = 7'b1000000; //0 
    4'd1 : segm = 7'b1111001; //1 
    4'd2 : segm = 7'b0100100; //2 
    4'd3 : segm = 7'b0110000; //3 
    4'd4 : segm = 7'b0011001; //4 
    4'd5 : segm = 7'b0010010; //5 
    4'd6 : segm = 7'b0000010; //6 
    4'd7 : segm = 7'b1111000; //7 
    4'd8 : segm = 7'b0000000; //8 
    4'd9 : segm = 7'b0010000; //9 
    default : segm = 7'b1111111; 
    endcase 
end 

endmodule 

Answer 1

您可以強制計數器接近您的測試平臺中感興趣的值。 你可以通過兩種風格。

1）強制計數器的值接近您的興趣併產生一些時鐘週期。

2）強制您感興趣的位並等待一些時鐘週期。

在這種情況下，'h1000和'h1000000值是感興趣的或位24和13。

// function to set the register - replace <DUT> 
task load_counter (reg [24:0] val); 
#1 <DUT>.q = val ; //delay is to overwrite the main counter 
endtask 

或

// function to set the counter bit - replace <DUT> 
task count_up (int count,int loc , bit val); 
repeat(count) @(posedge clock) ; 
#1 <DUT>.q[loc] = val; //delay is to overwrite the main counter 
endtask 

// toggle bit 24 and in between toggle bit 13 based on counts. 
// 100 clock is just a value it can be changes. 
task count_24(int count_24,int count_13); 
repeat (count_24) 
     begin 
     repeat(count_13) 
     begin 
       count_up (100,13,1); 
       count_up (100,13,0); 
     end 
     count_up (1,24,1); 
     repeat(count_13) 
     begin 
       count_up (100,13,1); 
       count_up (100,13,0); 
     end 
     count_up (1,24,0); 
end 
endtask 

在第一種方法

load_counter(25'hff0);// load and wait for bit 13 to be set 
repeat(50) @(posedge clock) ; 
load_counter(25'h1ff0); // load and wait for bit 13 to be re-set. 
repeat(50) @(posedge clock) ; 
load_counter(25'hf0ff0); //load and wait for bit 13 set (while other bits > 13 are on) 
repeat(50) @(posedge clock) ; 
load_counter(25'hfffff0); // bit 24 set 
repeat(50) @(posedge clock) ; 
// if needed add set/reset for bit 13 code here 
load_counter(25'h1fffff0); // load and wait till bit 24 rolls over 
repeat(50) @(posedge clock) ; 
// repeat the whole process above in a loop to get desired behavior 

你也可以隨機數量的13位切換，你需要每個時鐘的24個被觸發和數量之間看到

那需要在櫃檯變化之間運行。

在方案2中

的13和24的計數值可通過測試寫入器來確定，或者也可以被隨機化。

count_24(10,10) 

在選項1中，我們讓計數器機制完成大部分任務，因此是首選。

但最後它還更好地運行整個櫃檯看結果。大概你可以把它作爲週末迴歸來運行。

你也可以直接觀察TB中的信號。

wire [3:0] observe_unidad = <DUT>.unidad; 
wire [3:0] observe_decena = <DUT>.decena; 

添加完整的代碼在這裏一TB ...

// this code will not synthesize 
module tb_cont ; 


reg clock_gen ; // To generate a clock 
reg reset_gen ; // to generate reset 

// Main counter instance 
cont cont_instance (
       .clock(clock_gen), 
       .reset (reset_gen) 
       ) ; 

// Clock generation block 
initial 
begin 
clock_gen = 0 ; 

forever 
begin 
     #10 clock_gen = 0 ; 
     #10 clock_gen = 1 ; 
end 
end 

// Task to write data in the cont- block 
task count_up (int count,int loc , bit val); 
repeat(count) @(posedge clock_gen) ; 
#1 cont_instance.q[loc] = val; //delay is to overwrite themain counter 
endtask 

/toggle bit 24 and in between toggle bit 13 based on counts. 
// 100 clock is just a value it can be changed. 
task count_24(int count_24,int count_13); 
repeat (count_24) 
     begin 
     repeat(count_13) 
     begin 
       count_up (100,13,1); 
       count_up (100,13,0); 
     end 
     count_up (1,24,1); 
     repeat(count_13) 
     begin 
       count_up (100,13,1); 
       count_up (100,13,0); 
     end 
     count_up (1,24,0); 
end 
endtask 

// task to load the counter 
task load_counter (reg [24:0] val); 
#1 cont_instance.q = val ; //delay is to overwrite themain counter 
endtask 


initial 
begin 
// dump waveform to observe signals 
$dumpvars; 

// generate a reset first 
reset_gen = 0 ; 
#100 reset_gen = 0 ; 
#100 reset_gen = 1 ; 
#100 ; 
@(posedge clock_gen) ; 
reset_gen = 0 ; 
end 

// value for the count 
int count13 = 100; 
int count24=100; 

// generate test vector 
initial 
begin 

repeat(100) @ (posedge clock_gen) ; // wait for counter 
load_counter(25'hff0); 
repeat(100) @ (posedge clock_gen) ; // wait for counter 
load_counter(25'hfffff0); 
repeat(100) @ (posedge clock_gen) ; // wait for counter 
load_counter(25'h1fffff0); 
repeat(100) @ (posedge clock_gen) ; // wait for counter 

// scheme 2 
count_24(10,10); 

$finish ; 
end 

// both the signal can eb observed 
wire [3:0] observe_unidad = cont_instance.unidad; 
wire [3:0] observe_decena = cont_instance.decena; 

endmodule