VHDL - 設計庫不包含單位

Question

我有以下結構：上線Error (10481): VHDL Use Clause error at DE2_TOP.vhd(276): design library "work" does not contain primary unit "lab1"：

architecture datapath of DE2_TOP is 
begin 
U1: entity work.lab1 port map (
    clock => clock_50, 
    key => key, 
    hex6 => hex6, 
    hex5 => hex5, 
    hex4 => hex4 
); 
end datapath; 

我收到以下錯誤U1: entity work.lab1 port map (。任何人都知道是什麼導

Answer 1

您需要編譯至少entity爲lab1編譯DE2_TOP