VHDL for循環在測試臺上運行真值表

Question

我該如何在VHDL測試平臺上運行多路複用器的真值表。我在正確的軌道上嗎？

sel <= "00" after 100 ns, "01" after 200 ns, "10" after 300 ns, "11" after 400; 

process (sel) 
    variable p :STD_LOGIC_VECTOR(3 downto 0); 
begin 
    p := "0000" 
    for j in "0001" to "1111" loop 
     if j /= "1111" then p:= p + 1; 
     wait for 5 ns; 
    end loop ; 
end process; 

x <= p; 

Answer 1

保持生成的sel（選擇）和p（數據）一起，因爲很容易 與右定時以產生如果這些未在不同 受讓人或進程解耦。循環可以基於自然範圍創建。 過程然後可以是：

library ieee; 
use ieee.std_logic_1164.all; 
use ieee.numeric_std.all; 
... 
process is 
begin 
    for sel_loop in 0 to 2 ** sel'length - 1 loop -- 0 to 3 for sel'length = 2 
    for p_loop in 0 to 2 ** p'length - 1 loop -- 0 to 15 for p'length = 4 
     sel <= std_logic_vector(to_unsigned(sel_loop, sel'length)); 
     p <= std_logic_vector(to_unsigned(p_loop, p'length)); 
     wait for 5 ns; 
    end loop; 
    end loop; 
    wait; 
end process; 

波形如下。